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![]() The VNCSI_IFMD register controls the data expansion mode and the channel routing between the CSI-2 receivers and VIN instances. According to the chip manual revision 2.20 not all fields are available for all the SoCs: - V3M, V3H and E3 do not support the DES1 field has they do not feature a CSI20 receiver. - D3 only supports parallel input, and the whole register shall always be written as 0. Inspect the per-SoC channel routing table where the available CSI-2 instances are reported and configure VNCSI_IFMD accordingly. This patch supports this BSP change commit: https://github.com/renesas-rcar/linux-bsp/commit/f54697394457 ("media: rcar-vin: Fix VnCSI_IFMD register access for r8a77990") [hverkuil: replace BSP commit ID with BSP URL] Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Suggested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> |
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am437x | ||
atmel | ||
cadence | ||
coda | ||
davinci | ||
exynos-gsc | ||
exynos4-is | ||
marvell-ccic | ||
meson/ge2d | ||
mtk-jpeg | ||
mtk-mdp | ||
mtk-vcodec | ||
mtk-vpu | ||
omap | ||
omap3isp | ||
qcom | ||
rcar-vin | ||
rockchip | ||
s3c-camif | ||
s5p-g2d | ||
s5p-jpeg | ||
s5p-mfc | ||
sti | ||
stm32 | ||
sunxi | ||
ti-vpe | ||
vsp1 | ||
xilinx | ||
aspeed-video.c | ||
fsl-viu.c | ||
imx-pxp.c | ||
imx-pxp.h | ||
Kconfig | ||
m2m-deinterlace.c | ||
Makefile | ||
mx2_emmaprp.c | ||
pxa_camera.c | ||
rcar-fcp.c | ||
rcar_drif.c | ||
rcar_fdp1.c | ||
rcar_jpu.c | ||
renesas-ceu.c | ||
sh_vou.c | ||
via-camera.c | ||
via-camera.h | ||
video-mux.c |