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Document Renesas versa3 clock generator(5P35023) bindings. The 5P35023 is a VersaClock programmable clock generator and is designed for low-power, consumer, and high-performance PCI Express applications. The 5P35023 device is a three PLL architecture design, and each PLL is individually programmable and allowing for up to 6 unique frequency outputs. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230705171000.85786-2-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
86 lines
2.6 KiB
YAML
86 lines
2.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/renesas,5p35023.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas 5p35023 VersaClock 3 programmable I2C clock generator
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maintainers:
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- Biju Das <biju.das.jz@bp.renesas.com>
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description: |
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The 5P35023 is a VersaClock programmable clock generator and
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is designed for low-power, consumer, and high-performance PCI
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express applications. The 5P35023 device is a three PLL
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architecture design, and each PLL is individually programmable
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and allowing for up to 6 unique frequency outputs.
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An internal OTP memory allows the user to store the configuration
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in the device. After power up, the user can change the device register
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settings through the I2C interface when I2C mode is selected.
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The driver can read a full register map from the DT, and will use that
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register map to initialize the attached part (via I2C) when the system
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boots. Any configuration not supported by the common clock framework
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must be done via the full register map, including optimized settings.
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Link to datasheet:
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https://www.renesas.com/us/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3s-programmable-clock-generator
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properties:
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compatible:
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enum:
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- renesas,5p35023
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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clocks:
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maxItems: 1
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renesas,settings:
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description: Optional, complete register map of the device.
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Optimized settings for the device must be provided in full
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and are written during initialization.
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$ref: /schemas/types.yaml#/definitions/uint8-array
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maxItems: 37
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required:
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- compatible
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- reg
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- '#clock-cells'
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- clocks
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additionalProperties: false
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examples:
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- |
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i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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versa3: clock-generator@68 {
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compatible = "renesas,5p35023";
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reg = <0x68>;
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#clock-cells = <1>;
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clocks = <&x1_x2>;
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renesas,settings = [
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80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
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00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
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80 b0 45 c4 95
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];
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assigned-clocks = <&versa3 0>, <&versa3 1>,
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<&versa3 2>, <&versa3 3>,
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<&versa3 4>, <&versa3 5>;
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assigned-clock-rates = <12288000>, <25000000>,
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<12000000>, <11289600>,
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<11289600>, <24000000>;
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};
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};
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