Aric Cyr f7fb81a18f drm/amd/display: Check for flip pending before locking pipes ... [Why] When running games or benchmarking with v-sync disabled, disabling a plane (which is v-sync) can cause underflow. This is caused by flips pending before pipe locking being applied after locks are released and pipes could have been re-arranged or disconnected. This could potentially apply a flip on incorrect pipe. Also, previous logic of always locking pipes was unnecessary. [How] Only lock the pipes when there is a pipe being disabled to increase efficiency. Before the pipes are locked, check that any pending flips are cleared to ensure the flips are applied to the correct pipe. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-10-05 15:16:11 -04:00
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hw	drm/amd/display: Add dcn3.01 support to DC (v2)	2020-10-05 15:15:56 -04:00
bw_fixed.h
clock_source.h
compressor.h
core_status.h	drm/amd/display: Add helper to convert DC status	2020-07-01 01:59:20 -04:00
core_types.h	drm/amd/display: Calc DLG from dummy p-state if full p-state unsupported	2020-09-29 16:08:50 -04:00
custom_float.h
dc_link_ddc.h	drm/amd/display: DP link layer test 4.2.1.1 fix due to specs update	2020-07-01 01:59:26 -04:00
dc_link_dp.h	drm/amd/display: DP link layer test 4.2.1.1 fix due to specs update	2020-07-01 01:59:26 -04:00
dce_calcs.h
dcn_calc_math.h
dcn_calcs.h
hw_sequencer.h	drm/amd/display: Check for flip pending before locking pipes	2020-10-05 15:16:11 -04:00
hw_sequencer_private.h
link_hwss.h
reg_helper.h
resource.h	drm/amd/display: Add DCN3 Resource	2020-07-01 01:59:15 -04:00
vm_helper.h