linux/drivers/gpu/drm/amd/display
Jun Lei f7f38ffef5 drm/amd/display: fixup DPP programming sequence
[why]
DC does not correct account for the fact that DPP DTO is double buffered while DPP ref is not.
This means that when DPP ref clock is lowered when it's "safe to lower", the DPP blocks that need
an increased divider will temporarily have actual DPP clock drop below minimum while DTO
double buffering takes effect.  This results in temporary underflow.

[how]
To fix this, DPP clock cannot be programmed atomically, but rather be broken up into the DTO and the
ref.  Each has a separate "safe to lower" logic.  When doing "prepare" the ref and dividers may only increase.
When doing "optimize", both may decrease.  It is guaranteed that we won't exceed max DPP clock because
we do not use dividers larger than 1.

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15 10:53:43 -05:00
..
amdgpu_dm Merge tag 'drm-next-5.4-2019-08-09' of git://people.freedesktop.org/~agd5f/linux into drm-next 2019-08-12 14:20:21 +10:00
dc drm/amd/display: fixup DPP programming sequence 2019-08-15 10:53:43 -05:00
include drm/amd/display: Add ASICREV_IS_NAVI macros 2019-08-02 10:30:41 -05:00
modules drm/amd/display: Add 22, 24, and 26 degamma 2019-08-15 10:53:18 -05:00
Kconfig drm/amd/display: Add drm_audio_component support to amdgpu_dm 2019-07-11 14:37:24 -05:00
Makefile drm/amd/display: move clk_mgr files to right place 2019-05-31 10:39:31 -05:00
TODO