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Archana Patni f78bf066ac platform/x86: intel_pmc_core: Change Jasper Lake S0ix debug reg map back to ICL 
Jasper Lake uses Icelake PCH IPs and the S0ix debug interfaces are same as
Icelake. It uses SLP_S0_DBG register latch/read interface from Icelake
generation. It doesn't use Tiger Lake LPM debug registers. Change the
Jasper Lake S0ix debug interface to use the ICL reg map.

Fixes: 16292bed9c ("platform/x86: intel_pmc_core: Add Atom based Jasper Lake (JSL) platform support")
Signed-off-by: Archana Patni <archana.patni@intel.com>
Acked-by: David E. Box <david.e.box@intel.com>
Tested-by: Divagar Mohandass <divagar.mohandass@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-04-24 12:45:18 +03:00
..
chrome platform/chrome: cros_ec_sensorhub: Add missing '\n' in log messages 2020-04-13 16:31:33 +02:00
goldfish mm, tree-wide: rename put_user_page*() to unpin_user_page*() 2020-01-31 10:30:38 -08:00
mellanox platform/mellanox: mlxreg-hotplug: Add support for new capability register 2020-01-13 21:02:46 +02:00
mips MIPS: Kconfig: Use correct form for 'depends on' 2019-12-02 10:51:01 -08:00
olpc Platform: OLPC: add SPI MODULE_DEVICE_TABLE 2019-07-25 20:21:00 +03:00
x86 platform/x86: intel_pmc_core: Change Jasper Lake S0ix debug reg map back to ICL 2020-04-24 12:45:18 +03:00
Kconfig
Makefile