linux/drivers/gpu/drm/amd/include
Jude Shih f066af882b drm/amdgpu: add DMUB outbox event IRQ source define/complete/debug flag
[Why & How]
We use outbox interrupt that allows us to do the AUX via DMUB
Therefore, we need to add some irq source related definition
in the header files;

Signed-off-by: Jude Shih <shenshih@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09 16:54:42 -04:00
..
asic_reg drm/amd/amdgpu: Add CP_IB1_BASE_* to gc_10_3_0 headers 2021-04-09 16:46:59 -04:00
ivsrcid drm/amdgpu: add DMUB outbox event IRQ source define/complete/debug flag 2021-04-09 16:54:42 -04:00
aldebaran_ip_offset.h drm/amd/include: add ip offset header for aldebaran (v5) 2021-03-10 00:01:29 -05:00
amd_acpi.h
amd_pcie.h drm/amdgpu:Add pcie gen5 support in pcie capability. 2021-01-21 09:54:56 -05:00
amd_pcie_helpers.h
amd_shared.h drm/amd/pm: enable DCS 2021-02-09 15:27:57 -05:00
arct_ip_offset.h drm/amd/include/arct_ip_offset: Mark top-level IP_BASE definition as __maybe_unused 2020-11-24 12:09:53 -05:00
atom-bits.h
atom-names.h
atom-types.h
atombios.h drm/amd: Fix a typo in two different sentences 2021-04-09 16:44:32 -04:00
atomfirmware.h drm/amd/display: Interface for LTTPR interop 2021-04-09 16:48:25 -04:00
atomfirmwareid.h
cgs_common.h
cik_structs.h
dimgrey_cavefish_ip_offset.h drm/amd/include/dimgrey_cavefish_ip_offset: Mark top-level IP_BASE as __maybe_unused 2020-11-24 12:09:53 -05:00
discovery.h
displayobject.h
dm_pp_interface.h
kgd_kfd_interface.h
kgd_pp_interface.h drm/amd/pm: make DAL communicate with SMU through unified interfaces 2021-04-09 16:42:37 -04:00
navi10_enum.h
navi10_ip_offset.h drm/amd/include/navi10_ip_offset: Mark top-level IP_BASE as __maybe_unused 2020-11-24 12:09:53 -05:00
navi12_ip_offset.h drm/amd/include/navi12_ip_offset: Mark top-level IP_BASE as __maybe_unused 2020-11-24 12:09:53 -05:00
navi14_ip_offset.h drm/amd/include/navi14_ip_offset: Mark top-level IP_BASE as __maybe_unused 2020-11-24 12:09:53 -05:00
pptable.h
renoir_ip_offset.h drm/amd/include/renoir_ip_offset: Mark top-level IP_BASE as __maybe_unused 2021-01-14 13:20:20 -05:00
sienna_cichlid_ip_offset.h drm/amd/include/sienna_cichlid_ip_offset: Mark top-level IP_BASE as __maybe_unused 2020-11-24 12:09:53 -05:00
soc15_hw_ip.h
soc15_ih_clientid.h drm/amdgpu: Fix IH client ID naming table 2021-03-23 22:53:22 -04:00
v9_structs.h
v10_structs.h
vangogh_ip_offset.h drm/amd/include/vangogh_ip_offset: Mark top-level IP_BASE as __maybe_unused 2020-11-24 12:09:53 -05:00
vega10_enum.h
vega10_ip_offset.h
vega20_ip_offset.h drm/amd/include/vega20_ip_offset: Mark top-level IP_BASE definition as __maybe_unused 2020-11-24 12:09:53 -05:00
vi_structs.h drm/amdkfd: Check HIQ's MQD for queue preemption status 2021-03-23 22:59:25 -04:00