linux/arch/x86/kernel/cpu/resctrl
Reinette Chatre f3d44f18b0 x86/resctrl: Support CPUID enumeration of MBM counter width
The original Memory Bandwidth Monitoring (MBM) architectural
definition defines counters of up to 62 bits in the
IA32_QM_CTR MSR while the first-generation MBM implementation
uses statically defined 24 bit counters.

Expand the MBM CPUID enumeration properties to include the MBM
counter width. The previously undefined EAX output register contains,
in bits [7:0], the MBM counter width encoded as an offset from
24 bits. Enumerating this property is only specified for Intel
CPUs.

Suggested-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/afa3af2f753f6bc301fb743bc8944e749cb24afa.1588715690.git.reinette.chatre@intel.com
2020-05-06 18:02:41 +02:00
..
core.c x86/resctrl: Support CPUID enumeration of MBM counter width 2020-05-06 18:02:41 +02:00
ctrlmondata.c x86/resctrl: Maintain MBM counter width per resource 2020-05-06 18:00:35 +02:00
internal.h x86/resctrl: Maintain MBM counter width per resource 2020-05-06 18:00:35 +02:00
Makefile
monitor.c x86/resctrl: Maintain MBM counter width per resource 2020-05-06 18:00:35 +02:00
pseudo_lock.c x86/resctrl: Rename asm/resctrl_sched.h to asm/resctrl.h 2020-05-06 17:45:22 +02:00
pseudo_lock_event.h
rdtgroup.c x86/resctrl: Maintain MBM counter width per resource 2020-05-06 18:00:35 +02:00