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f43feef4e6
The ECC bit positions that describe whether the ECC interrupt is for Tx, Rx or descriptor memory and whether the it is a single correctable or double detected error were defined in incorrectly (reversed order). Fix the bit position definitions for these settings so that the proper ECC handling is performed. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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| .. | ||
| xgbe | ||
| 7990.c | ||
| 7990.h | ||
| a2065.c | ||
| a2065.h | ||
| am79c961a.c | ||
| am79c961a.h | ||
| amd8111e.c | ||
| amd8111e.h | ||
| ariadne.c | ||
| ariadne.h | ||
| atarilance.c | ||
| au1000_eth.c | ||
| au1000_eth.h | ||
| declance.c | ||
| hplance.c | ||
| hplance.h | ||
| Kconfig | ||
| lance.c | ||
| Makefile | ||
| mvme147.c | ||
| ni65.c | ||
| ni65.h | ||
| nmclan_cs.c | ||
| pcnet32.c | ||
| sun3lance.c | ||
| sunlance.c | ||