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154fcf3a78
To clean up the per CPU insanity of UP which causes sparse to be rightfully unhappy and prevents the usage of the generic per CPU accessors on cpu_info it is necessary to include <linux/percpu.h> into <asm/msr.h>. Including <linux/percpu.h> into <asm/msr.h> is impossible because it ends up in header dependency hell. The problem is that <asm/processor.h> includes <asm/msr.h>. The inclusion of <linux/percpu.h> results in a compile fail where the compiler cannot longer handle an include in <asm/cpufeature.h> which references boot_cpu_data which is defined in <asm/processor.h>. The only reason why <asm/msr.h> is included in <asm/processor.h> are the set/get_debugctlmsr() inlines. They are defined there because <asm/processor.h> is such a nice dump ground for everything. In fact they belong obviously into <asm/debugreg.h>. Move them to <asm/debugreg.h> and fix up the resulting damage which is just exposing the reliance on random include chains. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20240304005104.454678686@linutronix.de
84 lines
1.9 KiB
C
84 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Intel PCONFIG instruction support.
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*
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* Copyright (C) 2017 Intel Corporation
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*
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* Author:
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* Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
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*/
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#include <linux/bug.h>
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#include <linux/limits.h>
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#include <asm/cpufeature.h>
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#include <asm/intel_pconfig.h>
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#define PCONFIG_CPUID 0x1b
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#define PCONFIG_CPUID_SUBLEAF_MASK ((1 << 12) - 1)
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/* Subleaf type (EAX) for PCONFIG CPUID leaf (0x1B) */
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enum {
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PCONFIG_CPUID_SUBLEAF_INVALID = 0,
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PCONFIG_CPUID_SUBLEAF_TARGETID = 1,
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};
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/* Bitmask of supported targets */
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static u64 targets_supported __read_mostly;
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int pconfig_target_supported(enum pconfig_target target)
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{
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/*
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* We would need to re-think the implementation once we get > 64
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* PCONFIG targets. Spec allows up to 2^32 targets.
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*/
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BUILD_BUG_ON(PCONFIG_TARGET_NR >= 64);
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if (WARN_ON_ONCE(target >= 64))
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return 0;
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return targets_supported & (1ULL << target);
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}
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static int __init intel_pconfig_init(void)
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{
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int subleaf;
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if (!boot_cpu_has(X86_FEATURE_PCONFIG))
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return 0;
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/*
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* Scan subleafs of PCONFIG CPUID leaf.
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*
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* Subleafs of the same type need not to be consecutive.
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*
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* Stop on the first invalid subleaf type. All subleafs after the first
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* invalid are invalid too.
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*/
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for (subleaf = 0; subleaf < INT_MAX; subleaf++) {
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struct cpuid_regs regs;
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cpuid_count(PCONFIG_CPUID, subleaf,
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®s.eax, ®s.ebx, ®s.ecx, ®s.edx);
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switch (regs.eax & PCONFIG_CPUID_SUBLEAF_MASK) {
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case PCONFIG_CPUID_SUBLEAF_INVALID:
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/* Stop on the first invalid subleaf */
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goto out;
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case PCONFIG_CPUID_SUBLEAF_TARGETID:
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/* Mark supported PCONFIG targets */
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if (regs.ebx < 64)
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targets_supported |= (1ULL << regs.ebx);
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if (regs.ecx < 64)
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targets_supported |= (1ULL << regs.ecx);
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if (regs.edx < 64)
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targets_supported |= (1ULL << regs.edx);
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break;
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default:
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/* Unknown CPUID.PCONFIG subleaf: ignore */
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break;
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}
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}
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out:
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return 0;
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}
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arch_initcall(intel_pconfig_init);
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