mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-08-05 16:54:27 +00:00
724ba67515
The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Paul Barker <paul.barker@sancloud.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Nick Hawkins <nick.hawkins@hpe.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Romain Perier <romain.perier@gmail.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
450 lines
9.6 KiB
Text
450 lines
9.6 KiB
Text
/*
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* Copyright (C) 2015, 2016 Zodiac Inflight Innovations
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*
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* Based on an original 'vf610-twr.dts' which is Copyright 2015,
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* Freescale Semiconductor, Inc.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "vf610.dtsi"
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/ {
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x20000000>;
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};
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gpio-leds {
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compatible = "gpio-leds";
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pinctrl-0 = <&pinctrl_leds_debug>;
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pinctrl-names = "default";
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led-debug {
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label = "zii:green:debug1";
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gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
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compatible = "regulator-fixed";
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regulator-name = "vcc_3v3_mcu";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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usb0_vbus: regulator-usb0-vbus {
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compatible = "regulator-fixed";
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pinctrl-0 = <&pinctrl_usb_vbus>;
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regulator-name = "usb_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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regulator-always-on;
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regulator-boot-on;
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gpio = <&gpio0 6 0>;
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};
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supply-voltage-monitor {
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compatible = "iio-hwmon";
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io-channels = <&adc0 8>, /* VCC_1V5 */
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<&adc0 9>, /* VCC_1V8 */
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<&adc1 8>, /* VCC_1V0 */
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<&adc1 9>; /* VCC_1V2 */
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};
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};
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&adc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_adc0_ad5>;
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vref-supply = <®_vcc_3v3_mcu>;
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status = "okay";
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};
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&edma0 {
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status = "okay";
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};
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&edma1 {
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status = "okay";
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};
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&esdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc1>;
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bus-width = <4>;
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status = "okay";
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};
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&fec0 {
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phy-mode = "rmii";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec0>;
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status = "okay";
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};
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&fec1 {
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phy-mode = "rmii";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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status = "okay";
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fixed-link {
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speed = <100>;
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full-duplex;
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};
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mdio1: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <12500000>;
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suppress-preamble;
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status = "okay";
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};
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};
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&i2c0 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c0>;
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pinctrl-1 = <&pinctrl_i2c0_gpio>;
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scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
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status = "okay";
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lm75@48 {
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compatible = "national,lm75";
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reg = <0x48>;
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};
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eeprom@50 {
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compatible = "atmel,24c04";
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reg = <0x50>;
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};
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eeprom@52 {
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compatible = "atmel,24c04";
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reg = <0x52>;
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};
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ds1682@6b {
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compatible = "dallas,ds1682";
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reg = <0x6b>;
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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};
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&qspi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi0>;
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status = "okay";
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/*
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* Attached MT25QL02 can go up to 90Mhz in DTR and 166 in STR
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* modes, so, spi-max-frequency is limited to 90MHz
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*/
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flash@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <90000000>;
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spi-rx-bus-width = <4>;
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reg = <0>;
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m25p,fast-read;
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};
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flash@2 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <90000000>;
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spi-rx-bus-width = <4>;
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reg = <2>;
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m25p,fast-read;
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&usbdev0 {
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disable-over-current;
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vbus-supply = <&usb0_vbus>;
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dr_mode = "host";
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status = "okay";
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};
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&usbh1 {
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disable-over-current;
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status = "okay";
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};
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&usbmisc0 {
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status = "okay";
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};
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&usbmisc1 {
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status = "okay";
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};
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&usbphy0 {
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status = "okay";
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};
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&usbphy1 {
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status = "okay";
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};
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&tempsensor {
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io-channels = <&adc0 16>;
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};
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&iomuxc {
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pinctrl_adc0_ad5: adc0ad5grp {
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fsl,pins = <
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VF610_PAD_PTC30__ADC0_SE5 0x00a1
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>;
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};
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pinctrl_dspi0: dspi0grp {
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fsl,pins = <
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VF610_PAD_PTB18__DSPI0_CS1 0x1182
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VF610_PAD_PTB19__DSPI0_CS0 0x1182
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VF610_PAD_PTB20__DSPI0_SIN 0x1181
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VF610_PAD_PTB21__DSPI0_SOUT 0x1182
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VF610_PAD_PTB22__DSPI0_SCK 0x1182
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>;
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};
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pinctrl_dspi2: dspi2grp {
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fsl,pins = <
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VF610_PAD_PTD31__DSPI2_CS1 0x1182
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VF610_PAD_PTD30__DSPI2_CS0 0x1182
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VF610_PAD_PTD29__DSPI2_SIN 0x1181
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VF610_PAD_PTD28__DSPI2_SOUT 0x1182
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VF610_PAD_PTD27__DSPI2_SCK 0x1182
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>;
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};
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pinctrl_esdhc1: esdhc1grp {
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fsl,pins = <
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VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
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VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
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VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
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VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
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VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
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VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
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VF610_PAD_PTA7__GPIO_134 0x219d
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>;
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};
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pinctrl_fec0: fec0grp {
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fsl,pins = <
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VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d2
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VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d3
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VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1
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VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
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VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
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VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
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VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
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VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
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VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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VF610_PAD_PTA6__RMII_CLKIN 0x30d1
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VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
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VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
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VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
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VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
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VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
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VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
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VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
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VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
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VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
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>;
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};
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pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
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fsl,pins = <
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VF610_PAD_PTB22__GPIO_44 0x33e2
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VF610_PAD_PTB21__GPIO_43 0x33e2
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VF610_PAD_PTB20__GPIO_42 0x33e1
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VF610_PAD_PTB19__GPIO_41 0x33e2
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VF610_PAD_PTB18__GPIO_40 0x33e2
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>;
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};
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pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
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fsl,pins = <
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VF610_PAD_PTB5__GPIO_27 0x219d
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>;
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};
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pinctrl_gpio_switch1: pinctrl-gpio-switch1 {
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fsl,pins = <
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VF610_PAD_PTB4__GPIO_26 0x219d
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>;
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};
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pinctrl_i2c_mux_reset: pinctrl-i2c-mux-reset {
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fsl,pins = <
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VF610_PAD_PTE14__GPIO_119 0x31c2
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>;
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};
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pinctrl_i2c0: i2c0grp {
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fsl,pins = <
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VF610_PAD_PTB14__I2C0_SCL 0x37ff
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VF610_PAD_PTB15__I2C0_SDA 0x37ff
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>;
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};
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pinctrl_i2c0_gpio: i2c0grp-gpio {
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fsl,pins = <
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VF610_PAD_PTB14__GPIO_36 0x31c2
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VF610_PAD_PTB15__GPIO_37 0x31c2
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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VF610_PAD_PTB16__I2C1_SCL 0x37ff
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VF610_PAD_PTB17__I2C1_SDA 0x37ff
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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VF610_PAD_PTA22__I2C2_SCL 0x37ff
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VF610_PAD_PTA23__I2C2_SDA 0x37ff
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>;
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};
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pinctrl_leds_debug: pinctrl-leds-debug {
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fsl,pins = <
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VF610_PAD_PTD20__GPIO_74 0x31c2
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>;
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};
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pinctrl_qspi0: qspi0grp {
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fsl,pins = <
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VF610_PAD_PTD0__QSPI0_A_QSCK 0x38c2
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VF610_PAD_PTD1__QSPI0_A_CS0 0x38c2
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VF610_PAD_PTD2__QSPI0_A_DATA3 0x38c3
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VF610_PAD_PTD3__QSPI0_A_DATA2 0x38c3
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VF610_PAD_PTD4__QSPI0_A_DATA1 0x38c3
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VF610_PAD_PTD5__QSPI0_A_DATA0 0x38c3
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VF610_PAD_PTD7__QSPI0_B_QSCK 0x38c2
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VF610_PAD_PTD8__QSPI0_B_CS0 0x38c2
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VF610_PAD_PTD9__QSPI0_B_DATA3 0x38c3
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VF610_PAD_PTD10__QSPI0_B_DATA2 0x38c3
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VF610_PAD_PTD11__QSPI0_B_DATA1 0x38c3
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VF610_PAD_PTD12__QSPI0_B_DATA0 0x38c3
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>;
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};
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pinctrl_uart0: uart0grp {
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fsl,pins = <
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VF610_PAD_PTB10__UART0_TX 0x21a2
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VF610_PAD_PTB11__UART0_RX 0x21a1
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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VF610_PAD_PTB23__UART1_TX 0x21a2
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VF610_PAD_PTB24__UART1_RX 0x21a1
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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VF610_PAD_PTD23__UART2_TX 0x21a2
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VF610_PAD_PTD22__UART2_RX 0x21a1
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>;
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};
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pinctrl_usb_vbus: pinctrl-usb-vbus {
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fsl,pins = <
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VF610_PAD_PTA16__GPIO_6 0x31c2
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>;
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};
|
|
|
|
pinctrl_usb0_host: usb0-host-grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTD6__GPIO_85 0x0062
|
|
>;
|
|
};
|
|
};
|