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6ebbf2ce43
ARMv6 and greater introduced a new instruction ("bx") which can be used
to return from function calls. Recent CPUs perform better when the
"bx lr" instruction is used rather than the "mov pc, lr" instruction,
and this sequence is strongly recommended to be used by the ARM
architecture manual (section A.4.1.1).
We provide a new macro "ret" with all its variants for the condition
code which will resolve to the appropriate instruction.
Rather than doing this piecemeal, and miss some instances, change all
the "mov pc" instances to use the new macro, with the exception of
the "movs" instruction and the kprobes code. This allows us to detect
the "mov pc, lr" case and fix it up - and also gives us the possibility
of deploying this for other registers depending on the CPU selection.
Reported-by: Will Deacon <will.deacon@arm.com>
Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701_bootresume.S
Tested-by: Andrew Lunn <andrew@lunn.ch> # Kirkwood
Tested-by: Shawn Guo <shawn.guo@freescale.com>
Tested-by: Tony Lindgren <tony@atomide.com> # OMAPs
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> # Armada XP, 375, 385
Acked-by: Sekhar Nori <nsekhar@ti.com> # DaVinci
Acked-by: Christoffer Dall <christoffer.dall@linaro.org> # kvm/hyp
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> # PXA3xx
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> # Xen
Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> # ARMv7M
Tested-by: Simon Horman <horms+renesas@verge.net.au> # Shmobile
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
70 lines
1.8 KiB
ArmAsm
70 lines
1.8 KiB
ArmAsm
/*
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* linux/arch/arm/mm/tlb-fa.S
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*
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* Copyright (C) 2005 Faraday Corp.
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* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
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*
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* Based on tlb-v4wbi.S:
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* Copyright (C) 1997-2002 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* ARM architecture version 4, Faraday variation.
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* This assume an unified TLBs, with a write buffer, and branch target buffer (BTB)
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*
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* Processors: FA520 FA526 FA626
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/tlbflush.h>
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#include "proc-macros.S"
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/*
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* flush_user_tlb_range(start, end, mm)
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*
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* Invalidate a range of TLB entries in the specified address space.
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*
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* - start - range start address
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* - end - range end address
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* - mm - mm_struct describing address space
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*/
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.align 4
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ENTRY(fa_flush_user_tlb_range)
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vma_vm_mm ip, r2
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act_mm r3 @ get current->active_mm
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eors r3, ip, r3 @ == mm ?
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retne lr @ no, we dont do anything
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mov r3, #0
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mcr p15, 0, r3, c7, c10, 4 @ drain WB
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bic r0, r0, #0x0ff
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bic r0, r0, #0xf00
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1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
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add r0, r0, #PAGE_SZ
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cmp r0, r1
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blo 1b
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mcr p15, 0, r3, c7, c10, 4 @ data write barrier
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ret lr
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ENTRY(fa_flush_kern_tlb_range)
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mov r3, #0
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mcr p15, 0, r3, c7, c10, 4 @ drain WB
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bic r0, r0, #0x0ff
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bic r0, r0, #0xf00
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1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
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add r0, r0, #PAGE_SZ
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cmp r0, r1
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blo 1b
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mcr p15, 0, r3, c7, c10, 4 @ data write barrier
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mcr p15, 0, r3, c7, c5, 4 @ prefetch flush (isb)
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ret lr
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__INITDATA
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/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
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define_tlb_functions fa, fa_tlb_flags
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