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eac1ea2026
This patch implement routines (adjfine, adjtime, gettime and settime) for manipulating the chip's PTP clock. It registers the ptp caps to posix clock register. Signed-off-by: Christian Eggers <ceggers@arri.de> Co-developed-by: Arun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> # mostly api Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
52 lines
1.2 KiB
C
52 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Microchip KSZ PTP register definitions
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* Copyright (C) 2022 Microchip Technology Inc.
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*/
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#ifndef __KSZ_PTP_REGS_H
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#define __KSZ_PTP_REGS_H
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/* 5 - PTP Clock */
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#define REG_PTP_CLK_CTRL 0x0500
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#define PTP_STEP_ADJ BIT(6)
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#define PTP_STEP_DIR BIT(5)
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#define PTP_READ_TIME BIT(4)
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#define PTP_LOAD_TIME BIT(3)
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#define PTP_CLK_ADJ_ENABLE BIT(2)
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#define PTP_CLK_ENABLE BIT(1)
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#define PTP_CLK_RESET BIT(0)
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#define REG_PTP_RTC_SUB_NANOSEC__2 0x0502
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#define PTP_RTC_SUB_NANOSEC_M 0x0007
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#define PTP_RTC_0NS 0x00
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#define REG_PTP_RTC_NANOSEC 0x0504
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#define REG_PTP_RTC_SEC 0x0508
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#define REG_PTP_SUBNANOSEC_RATE 0x050C
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#define PTP_SUBNANOSEC_M 0x3FFFFFFF
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#define PTP_RATE_DIR BIT(31)
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#define PTP_TMP_RATE_ENABLE BIT(30)
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#define REG_PTP_SUBNANOSEC_RATE_L 0x050E
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#define REG_PTP_RATE_DURATION 0x0510
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#define REG_PTP_RATE_DURATION_H 0x0510
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#define REG_PTP_RATE_DURATION_L 0x0512
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#define REG_PTP_MSG_CONF1 0x0514
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#define PTP_802_1AS BIT(7)
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#define PTP_ENABLE BIT(6)
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#define PTP_ETH_ENABLE BIT(5)
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#define PTP_IPV4_UDP_ENABLE BIT(4)
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#define PTP_IPV6_UDP_ENABLE BIT(3)
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#define PTP_TC_P2P BIT(2)
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#define PTP_MASTER BIT(1)
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#define PTP_1STEP BIT(0)
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#endif
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