Lubomir Rintel ea56ad6026 clk: mmp2: Stop pretending PLL outputs are constant ... The hardcoded values for PLL1 and PLL2 are wrong. PLL1 is slightly off -- it defaults to 797.33 MHz, not 800 MHz. PLL2 is disabled by default, but also configurable. Tested on a MMP2-based OLPC XO-1.75 laptop, with PLL1=797.33 and various values of PLL2 set via set-pll2-520mhz, set-pll2-910mhz and set-pll2-988mhz Open Firmware words. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-6-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2020-03-20 18:19:31 -07:00
..
clk-apbc.c	clk: mmp: make clk_ops const	2017-11-01 23:25:47 -07:00
clk-apmu.c	clk: mmp: make clk_ops const	2017-11-01 23:25:47 -07:00
clk-frac.c	clk: let init callback return an error code	2019-12-23 18:53:13 -08:00
clk-gate.c	clk: Remove CLK_IS_BASIC clk flag	2019-04-26 10:40:49 -07:00
clk-mix.c	clk: mmp2: Constify some strings	2020-03-20 18:19:30 -07:00
clk-mmp2.c	clk: mmp: Adjust checks for NULL pointers	2017-11-13 17:41:17 -08:00
clk-of-mmp2.c	clk: mmp2: Stop pretending PLL outputs are constant	2020-03-20 18:19:31 -07:00
clk-of-pxa168.c
clk-of-pxa910.c
clk-of-pxa1928.c
clk-pll.c	clk: mmp2: Add support for PLL clock sources	2020-03-20 18:19:31 -07:00
clk-pxa168.c	clk: mmp: Adjust checks for NULL pointers	2017-11-13 17:41:17 -08:00
clk-pxa910.c	clk: mmp: Adjust checks for NULL pointers	2017-11-13 17:41:17 -08:00
clk.c	clk: mmp2: Add support for PLL clock sources	2020-03-20 18:19:31 -07:00
clk.h	clk: mmp2: Add support for PLL clock sources	2020-03-20 18:19:31 -07:00
Makefile	clk: mmp2: Add support for PLL clock sources	2020-03-20 18:19:31 -07:00
reset.c	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
reset.h	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00