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-----BEGIN PGP SIGNATURE----- iQJIBAABCgAyFiEEgMe7l+5h9hnxdsnuWYigwDrT+vwFAmLr+2wUHGJoZWxnYWFz QGdvb2dsZS5jb20ACgkQWYigwDrT+vxfZg//eChkC2EUdT6K3zuQDbJJhsGcuOQF lnZuUyDn4xw7BkEoZf8V6YdAnp7VvgKhLOq1/q3Geu/LBbCaczoEogOCaR/WcVOs C+MsN0RWZQtgfuZKncQoqp25NeLPK9PFToeiIX/xViAYZF7NVjDY7XQiZHQ6JkEA /7cUqv/4nS3KCMsKjfmiOxGnqohMWtICiw9qjFvJ40PEDnNB1b53rkiVTxBFePpI ePfsRfi/C7klE3xNfoiEgrPp+Jfw+oShsCwXUsId7bEL2oLBc7ClqP05ZYZD3bTK QQYyZ12Cq8TysciYpUGBjBnywUHS5DIO5YaV3wxyVAR2Z+6GY2/QVjOa2kKvoK0o Hba6TJf8bL58AhSI8Q62pBM0sS7dqJSff+9c2BGpZvII5spP/rQQLlJO56TJjwkw Dlf0d3thhZOc9vSKjKw+0v0FdAyc4L11EOwUsw95jZeT5WWgqJYGFnWPZwqBI1KM DI1E5wVO5tA2H3NEn+BTTHbLWL+UppqyXPXBHiW52b2q5Bt8fJWMsFvnEEjclxmG pYCI7VgF8jqbYKxjobxPFY2x6PH9hfaGMxwzZSdOX6e/Eh+1esgyyaC5APpCO+Pp e4OkJaOzCmggrD0jYeLWu+yDm5KRrYo5cdfKHrKgAof0Am41lAa1OhJ2iH4ckNqP 1qmHereDOe0zNVw= =9TAR -----END PGP SIGNATURE----- Merge tag 'pci-v5.20-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull pci updates from Bjorn Helgaas: "Enumeration: - Consolidate duplicated 'next function' scanning and extend to allow 'isolated functions' on s390, similar to existing hypervisors (Niklas Schnelle) Resource management: - Implement pci_iobar_pfn() for sparc, which allows us to remove the sparc-specific pci_mmap_page_range() and pci_mmap_resource_range(). This removes the ability to map the entire PCI I/O space using /proc/bus/pci, but we believe that's already been broken since v2.6.28 (Arnd Bergmann) - Move common PCI definitions to asm-generic/pci.h and rework others to be be more specific and more encapsulated in arches that need them (Stafford Horne) Power management: - Convert drivers to new *_PM_OPS macros to avoid need for '#ifdef CONFIG_PM_SLEEP' or '__maybe_unused' (Bjorn Helgaas) Virtualization: - Add ACS quirk for Broadcom BCM5750x multifunction NICs that isolate the functions but don't advertise an ACS capability (Pavan Chebbi) Error handling: - Clear PCI Status register during enumeration in case firmware left errors logged (Kai-Heng Feng) - When we have native control of AER, enable error reporting for all devices that support AER. Previously only a few drivers enabled this (Stefan Roese) - Keep AER error reporting enabled for switches. Previously we enabled this during enumeration but immediately disabled it (Stefan Roese) - Iterate over error counters instead of error strings to avoid printing junk in AER sysfs counters (Mohamed Khalfella) ASPM: - Remove pcie_aspm_pm_state_change() so ASPM config changes, e.g., via sysfs, are not lost across power state changes (Kai-Heng Feng) Endpoint framework: - Don't stop an EPC when unbinding an EPF from it (Shunsuke Mie) Endpoint embedded DMA controller driver: - Simplify and clean up support for the DesignWare embedded DMA (eDMA) controller (Frank Li, Serge Semin) Broadcom STB PCIe controller driver: - Avoid config space accesses when link is down because we can't recover from the CPU aborts these cause (Jim Quinlan) - Look for power regulators described under Root Ports in DT and enable them before scanning the secondary bus (Jim Quinlan) - Disable/enable regulators in suspend/resume (Jim Quinlan) Freescale i.MX6 PCIe controller driver: - Simplify and clean up clock and PHY management (Richard Zhu) - Disable/enable regulators in suspend/resume (Richard Zhu) - Set PCIE_DBI_RO_WR_EN before writing DBI registers (Richard Zhu) - Allow speeds faster than Gen2 (Richard Zhu) - Make link being down a non-fatal error so controller probe doesn't fail if there are no Endpoints connected (Richard Zhu) Loongson PCIe controller driver: - Add ACPI and MCFG support for Loongson LS7A (Huacai Chen) - Avoid config reads to non-existent LS2K/LS7A devices because a hardware defect causes machine hangs (Huacai Chen) - Work around LS7A integrated devices that report incorrect Interrupt Pin values (Jianmin Lv) Marvell Aardvark PCIe controller driver: - Add support for AER and Slot capability on emulated bridge (Pali Rohár) MediaTek PCIe controller driver: - Add Airoha EN7532 to DT binding (John Crispin) - Allow building of driver for ARCH_AIROHA (Felix Fietkau) MediaTek PCIe Gen3 controller driver: - Print decoded LTSSM state when the link doesn't come up (Jianjun Wang) NVIDIA Tegra194 PCIe controller driver: - Convert DT binding to json-schema (Vidya Sagar) - Add DT bindings and driver support for Tegra234 Root Port and Endpoint mode (Vidya Sagar) - Fix some Root Port interrupt handling issues (Vidya Sagar) - Set default Max Payload Size to 256 bytes (Vidya Sagar) - Fix Data Link Feature capability programming (Vidya Sagar) - Extend Endpoint mode support to devices beyond Controller-5 (Vidya Sagar) Qualcomm PCIe controller driver: - Rework clock, reset, PHY power-on ordering to avoid hangs and improve consistency (Robert Marko, Christian Marangi) - Move pipe_clk handling to PHY drivers (Dmitry Baryshkov) - Add IPQ60xx support (Selvam Sathappan Periakaruppan) - Allow ASPM L1 and substates for 2.7.0 (Krishna chaitanya chundru) - Add support for more than 32 MSI interrupts (Dmitry Baryshkov) Renesas R-Car PCIe controller driver: - Convert DT binding to json-schema (Herve Codina) - Add Renesas RZ/N1D (R9A06G032) to rcar-gen2 DT binding and driver (Herve Codina) Samsung Exynos PCIe controller driver: - Fix phy-exynos-pcie driver so it follows the 'phy_init() before phy_power_on()' PHY programming model (Marek Szyprowski) Synopsys DesignWare PCIe controller driver: - Simplify and clean up the DWC core extensively (Serge Semin) - Fix an issue with programming the ATU for regions that cross a 4GB boundary (Serge Semin) - Enable the CDM check if 'snps,enable-cdm-check' exists; previously we skipped it if 'num-lanes' was absent (Serge Semin) - Allocate a 32-bit DMA-able page to be MSI target instead of using a driver data structure that may not be addressable with 32-bit address (Will McVicker) - Add DWC core support for more than 32 MSI interrupts (Dmitry Baryshkov) Xilinx Versal CPM PCIe controller driver: - Add DT binding and driver support for Versal CPM5 Gen5 Root Port (Bharat Kumar Gogada)" * tag 'pci-v5.20-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (150 commits) PCI: imx6: Support more than Gen2 speed link mode PCI: imx6: Set PCIE_DBI_RO_WR_EN before writing DBI registers PCI: imx6: Reformat suspend callback to keep symmetric with resume PCI: imx6: Move the imx6_pcie_ltssm_disable() earlier PCI: imx6: Disable clocks in reverse order of enable PCI: imx6: Do not hide PHY driver callbacks and refine the error handling PCI: imx6: Reduce resume time by only starting link if it was up before suspend PCI: imx6: Mark the link down as non-fatal error PCI: imx6: Move regulator enable out of imx6_pcie_deassert_core_reset() PCI: imx6: Turn off regulator when system is in suspend mode PCI: imx6: Call host init function directly in resume PCI: imx6: Disable i.MX6QDL clock when disabling ref clocks PCI: imx6: Propagate .host_init() errors to caller PCI: imx6: Collect clock enables in imx6_pcie_clk_enable() PCI: imx6: Factor out ref clock disable to match enable PCI: imx6: Move imx6_pcie_clk_disable() earlier PCI: imx6: Move imx6_pcie_enable_ref_clk() earlier PCI: imx6: Move PHY management functions together PCI: imx6: Move imx6_pcie_grp_offset(), imx6_pcie_configure_type() earlier PCI: imx6: Convert to NOIRQ_SYSTEM_SLEEP_PM_OPS() ...
146 lines
4.1 KiB
C
146 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_ARM_DMA_H
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#define __ASM_ARM_DMA_H
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/*
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* This is the maximum virtual address which can be DMA'd from.
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*/
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#ifndef CONFIG_ZONE_DMA
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#define MAX_DMA_ADDRESS 0xffffffffUL
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#else
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#define MAX_DMA_ADDRESS ({ \
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extern phys_addr_t arm_dma_zone_size; \
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arm_dma_zone_size && arm_dma_zone_size < (0x100000000ULL - PAGE_OFFSET) ? \
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(PAGE_OFFSET + arm_dma_zone_size) : 0xffffffffUL; })
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#endif
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#ifdef CONFIG_ISA_DMA_API
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/*
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* This is used to support drivers written for the x86 ISA DMA API.
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* It should not be re-used except for that purpose.
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*/
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#include <linux/spinlock.h>
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#include <linux/scatterlist.h>
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#include <mach/isa-dma.h>
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/*
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* The DMA modes reflect the settings for the ISA DMA controller
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*/
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#define DMA_MODE_MASK 0xcc
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#define DMA_MODE_READ 0x44
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#define DMA_MODE_WRITE 0x48
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#define DMA_MODE_CASCADE 0xc0
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#define DMA_AUTOINIT 0x10
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extern raw_spinlock_t dma_spin_lock;
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static inline unsigned long claim_dma_lock(void)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&dma_spin_lock, flags);
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return flags;
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}
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static inline void release_dma_lock(unsigned long flags)
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{
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raw_spin_unlock_irqrestore(&dma_spin_lock, flags);
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}
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/* Clear the 'DMA Pointer Flip Flop'.
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* Write 0 for LSB/MSB, 1 for MSB/LSB access.
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*/
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#define clear_dma_ff(chan)
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/* Set only the page register bits of the transfer address.
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*
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* NOTE: This is an architecture specific function, and should
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* be hidden from the drivers
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*/
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extern void set_dma_page(unsigned int chan, char pagenr);
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/* Request a DMA channel
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*
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* Some architectures may need to do allocate an interrupt
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*/
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extern int request_dma(unsigned int chan, const char * device_id);
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/* Free a DMA channel
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*
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* Some architectures may need to do free an interrupt
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*/
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extern void free_dma(unsigned int chan);
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/* Enable DMA for this channel
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*
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* On some architectures, this may have other side effects like
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* enabling an interrupt and setting the DMA registers.
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*/
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extern void enable_dma(unsigned int chan);
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/* Disable DMA for this channel
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*
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* On some architectures, this may have other side effects like
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* disabling an interrupt or whatever.
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*/
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extern void disable_dma(unsigned int chan);
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/* Test whether the specified channel has an active DMA transfer
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*/
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extern int dma_channel_active(unsigned int chan);
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/* Set the DMA scatter gather list for this channel
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*
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* This should not be called if a DMA channel is enabled,
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* especially since some DMA architectures don't update the
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* DMA address immediately, but defer it to the enable_dma().
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*/
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extern void set_dma_sg(unsigned int chan, struct scatterlist *sg, int nr_sg);
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/* Set the DMA address for this channel
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*
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* This should not be called if a DMA channel is enabled,
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* especially since some DMA architectures don't update the
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* DMA address immediately, but defer it to the enable_dma().
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*/
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extern void __set_dma_addr(unsigned int chan, void *addr);
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#define set_dma_addr(chan, addr) \
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__set_dma_addr(chan, (void *)__bus_to_virt(addr))
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/* Set the DMA byte count for this channel
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*
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* This should not be called if a DMA channel is enabled,
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* especially since some DMA architectures don't update the
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* DMA count immediately, but defer it to the enable_dma().
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*/
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extern void set_dma_count(unsigned int chan, unsigned long count);
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/* Set the transfer direction for this channel
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*
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* This should not be called if a DMA channel is enabled,
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* especially since some DMA architectures don't update the
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* DMA transfer direction immediately, but defer it to the
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* enable_dma().
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*/
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extern void set_dma_mode(unsigned int chan, unsigned int mode);
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/* Set the transfer speed for this channel
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*/
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extern void set_dma_speed(unsigned int chan, int cycle_ns);
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/* Get DMA residue count. After a DMA transfer, this
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* should return zero. Reading this while a DMA transfer is
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* still in progress will return unpredictable results.
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* If called before the channel has been used, it may return 1.
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* Otherwise, it returns the number of _bytes_ left to transfer.
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*/
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extern int get_dma_residue(unsigned int chan);
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#ifndef NO_DMA
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#define NO_DMA 255
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#endif
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#endif /* CONFIG_ISA_DMA_API */
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#endif /* __ASM_ARM_DMA_H */
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