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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-10-31 16:54:21 +00:00
e6f7d27df5
Return -ENOMEM from of_pci_prop_intr_map() if kcalloc() fails to prevent a
NULL pointer dereference in this case.
Fixes: 407d1a5192 ("PCI: Create device tree node for bridge")
Link: https://lore.kernel.org/r/20240303105729.78624-1-duoming@zju.edu.cn
Signed-off-by: Duoming Zhou <duoming@zju.edu.cn>
[bhelgaas: commit log]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
368 lines
8.8 KiB
C
368 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
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*/
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#include <linux/pci.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include "pci.h"
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#define OF_PCI_ADDRESS_CELLS 3
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#define OF_PCI_SIZE_CELLS 2
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#define OF_PCI_MAX_INT_PIN 4
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struct of_pci_addr_pair {
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u32 phys_addr[OF_PCI_ADDRESS_CELLS];
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u32 size[OF_PCI_SIZE_CELLS];
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};
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/*
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* Each entry in the ranges table is a tuple containing the child address,
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* the parent address, and the size of the region in the child address space.
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* Thus, for PCI, in each entry parent address is an address on the primary
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* side and the child address is the corresponding address on the secondary
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* side.
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*/
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struct of_pci_range {
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u32 child_addr[OF_PCI_ADDRESS_CELLS];
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u32 parent_addr[OF_PCI_ADDRESS_CELLS];
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u32 size[OF_PCI_SIZE_CELLS];
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};
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#define OF_PCI_ADDR_SPACE_IO 0x1
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#define OF_PCI_ADDR_SPACE_MEM32 0x2
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#define OF_PCI_ADDR_SPACE_MEM64 0x3
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#define OF_PCI_ADDR_FIELD_NONRELOC BIT(31)
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#define OF_PCI_ADDR_FIELD_SS GENMASK(25, 24)
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#define OF_PCI_ADDR_FIELD_PREFETCH BIT(30)
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#define OF_PCI_ADDR_FIELD_BUS GENMASK(23, 16)
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#define OF_PCI_ADDR_FIELD_DEV GENMASK(15, 11)
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#define OF_PCI_ADDR_FIELD_FUNC GENMASK(10, 8)
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#define OF_PCI_ADDR_FIELD_REG GENMASK(7, 0)
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enum of_pci_prop_compatible {
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PROP_COMPAT_PCI_VVVV_DDDD,
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PROP_COMPAT_PCICLASS_CCSSPP,
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PROP_COMPAT_PCICLASS_CCSS,
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PROP_COMPAT_NUM,
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};
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static void of_pci_set_address(struct pci_dev *pdev, u32 *prop, u64 addr,
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u32 reg_num, u32 flags, bool reloc)
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{
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prop[0] = FIELD_PREP(OF_PCI_ADDR_FIELD_BUS, pdev->bus->number) |
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FIELD_PREP(OF_PCI_ADDR_FIELD_DEV, PCI_SLOT(pdev->devfn)) |
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FIELD_PREP(OF_PCI_ADDR_FIELD_FUNC, PCI_FUNC(pdev->devfn));
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prop[0] |= flags | reg_num;
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if (!reloc) {
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prop[0] |= OF_PCI_ADDR_FIELD_NONRELOC;
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prop[1] = upper_32_bits(addr);
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prop[2] = lower_32_bits(addr);
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}
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}
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static int of_pci_get_addr_flags(struct resource *res, u32 *flags)
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{
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u32 ss;
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if (res->flags & IORESOURCE_IO)
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ss = OF_PCI_ADDR_SPACE_IO;
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else if (res->flags & IORESOURCE_MEM_64)
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ss = OF_PCI_ADDR_SPACE_MEM64;
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else if (res->flags & IORESOURCE_MEM)
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ss = OF_PCI_ADDR_SPACE_MEM32;
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else
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return -EINVAL;
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*flags = 0;
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if (res->flags & IORESOURCE_PREFETCH)
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*flags |= OF_PCI_ADDR_FIELD_PREFETCH;
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*flags |= FIELD_PREP(OF_PCI_ADDR_FIELD_SS, ss);
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return 0;
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}
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static int of_pci_prop_bus_range(struct pci_dev *pdev,
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struct of_changeset *ocs,
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struct device_node *np)
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{
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u32 bus_range[] = { pdev->subordinate->busn_res.start,
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pdev->subordinate->busn_res.end };
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return of_changeset_add_prop_u32_array(ocs, np, "bus-range", bus_range,
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ARRAY_SIZE(bus_range));
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}
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static int of_pci_prop_ranges(struct pci_dev *pdev, struct of_changeset *ocs,
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struct device_node *np)
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{
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struct of_pci_range *rp;
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struct resource *res;
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int i, j, ret;
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u32 flags, num;
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u64 val64;
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if (pci_is_bridge(pdev)) {
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num = PCI_BRIDGE_RESOURCE_NUM;
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res = &pdev->resource[PCI_BRIDGE_RESOURCES];
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} else {
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num = PCI_STD_NUM_BARS;
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res = &pdev->resource[PCI_STD_RESOURCES];
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}
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rp = kcalloc(num, sizeof(*rp), GFP_KERNEL);
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if (!rp)
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return -ENOMEM;
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for (i = 0, j = 0; j < num; j++) {
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if (!resource_size(&res[j]))
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continue;
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if (of_pci_get_addr_flags(&res[j], &flags))
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continue;
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val64 = res[j].start;
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of_pci_set_address(pdev, rp[i].parent_addr, val64, 0, flags,
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false);
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if (pci_is_bridge(pdev)) {
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memcpy(rp[i].child_addr, rp[i].parent_addr,
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sizeof(rp[i].child_addr));
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} else {
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/*
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* For endpoint device, the lower 64-bits of child
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* address is always zero.
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*/
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rp[i].child_addr[0] = j;
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}
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val64 = resource_size(&res[j]);
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rp[i].size[0] = upper_32_bits(val64);
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rp[i].size[1] = lower_32_bits(val64);
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i++;
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}
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ret = of_changeset_add_prop_u32_array(ocs, np, "ranges", (u32 *)rp,
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i * sizeof(*rp) / sizeof(u32));
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kfree(rp);
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return ret;
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}
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static int of_pci_prop_reg(struct pci_dev *pdev, struct of_changeset *ocs,
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struct device_node *np)
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{
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struct of_pci_addr_pair reg = { 0 };
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/* configuration space */
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of_pci_set_address(pdev, reg.phys_addr, 0, 0, 0, true);
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return of_changeset_add_prop_u32_array(ocs, np, "reg", (u32 *)®,
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sizeof(reg) / sizeof(u32));
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}
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static int of_pci_prop_interrupts(struct pci_dev *pdev,
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struct of_changeset *ocs,
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struct device_node *np)
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{
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int ret;
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u8 pin;
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ret = pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &pin);
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if (ret != 0)
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return ret;
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if (!pin)
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return 0;
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return of_changeset_add_prop_u32(ocs, np, "interrupts", (u32)pin);
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}
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static int of_pci_prop_intr_map(struct pci_dev *pdev, struct of_changeset *ocs,
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struct device_node *np)
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{
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u32 i, addr_sz[OF_PCI_MAX_INT_PIN] = { 0 }, map_sz = 0;
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struct of_phandle_args out_irq[OF_PCI_MAX_INT_PIN];
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__be32 laddr[OF_PCI_ADDRESS_CELLS] = { 0 };
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u32 int_map_mask[] = { 0xffff00, 0, 0, 7 };
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struct device_node *pnode;
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struct pci_dev *child;
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u32 *int_map, *mapp;
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int ret;
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u8 pin;
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pnode = pci_device_to_OF_node(pdev->bus->self);
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if (!pnode)
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pnode = pci_bus_to_OF_node(pdev->bus);
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if (!pnode) {
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pci_err(pdev, "failed to get parent device node");
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return -EINVAL;
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}
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laddr[0] = cpu_to_be32((pdev->bus->number << 16) | (pdev->devfn << 8));
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for (pin = 1; pin <= OF_PCI_MAX_INT_PIN; pin++) {
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i = pin - 1;
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out_irq[i].np = pnode;
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out_irq[i].args_count = 1;
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out_irq[i].args[0] = pin;
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ret = of_irq_parse_raw(laddr, &out_irq[i]);
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if (ret) {
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out_irq[i].np = NULL;
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pci_dbg(pdev, "parse irq %d failed, ret %d", pin, ret);
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continue;
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}
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of_property_read_u32(out_irq[i].np, "#address-cells",
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&addr_sz[i]);
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}
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list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
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for (pin = 1; pin <= OF_PCI_MAX_INT_PIN; pin++) {
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i = pci_swizzle_interrupt_pin(child, pin) - 1;
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if (!out_irq[i].np)
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continue;
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map_sz += 5 + addr_sz[i] + out_irq[i].args_count;
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}
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}
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/*
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* Parsing interrupt failed for all pins. In this case, it does not
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* need to generate interrupt-map property.
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*/
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if (!map_sz)
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return 0;
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int_map = kcalloc(map_sz, sizeof(u32), GFP_KERNEL);
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if (!int_map)
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return -ENOMEM;
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mapp = int_map;
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list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
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for (pin = 1; pin <= OF_PCI_MAX_INT_PIN; pin++) {
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i = pci_swizzle_interrupt_pin(child, pin) - 1;
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if (!out_irq[i].np)
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continue;
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*mapp = (child->bus->number << 16) |
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(child->devfn << 8);
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mapp += OF_PCI_ADDRESS_CELLS;
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*mapp = pin;
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mapp++;
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*mapp = out_irq[i].np->phandle;
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mapp++;
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if (addr_sz[i]) {
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ret = of_property_read_u32_array(out_irq[i].np,
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"reg", mapp,
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addr_sz[i]);
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if (ret)
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goto failed;
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}
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mapp += addr_sz[i];
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memcpy(mapp, out_irq[i].args,
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out_irq[i].args_count * sizeof(u32));
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mapp += out_irq[i].args_count;
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}
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}
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ret = of_changeset_add_prop_u32_array(ocs, np, "interrupt-map", int_map,
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map_sz);
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if (ret)
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goto failed;
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ret = of_changeset_add_prop_u32(ocs, np, "#interrupt-cells", 1);
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if (ret)
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goto failed;
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ret = of_changeset_add_prop_u32_array(ocs, np, "interrupt-map-mask",
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int_map_mask,
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ARRAY_SIZE(int_map_mask));
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if (ret)
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goto failed;
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kfree(int_map);
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return 0;
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failed:
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kfree(int_map);
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return ret;
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}
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static int of_pci_prop_compatible(struct pci_dev *pdev,
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struct of_changeset *ocs,
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struct device_node *np)
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{
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const char *compat_strs[PROP_COMPAT_NUM] = { 0 };
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int i, ret;
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compat_strs[PROP_COMPAT_PCI_VVVV_DDDD] =
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kasprintf(GFP_KERNEL, "pci%x,%x", pdev->vendor, pdev->device);
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compat_strs[PROP_COMPAT_PCICLASS_CCSSPP] =
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kasprintf(GFP_KERNEL, "pciclass,%06x", pdev->class);
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compat_strs[PROP_COMPAT_PCICLASS_CCSS] =
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kasprintf(GFP_KERNEL, "pciclass,%04x", pdev->class >> 8);
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ret = of_changeset_add_prop_string_array(ocs, np, "compatible",
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compat_strs, PROP_COMPAT_NUM);
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for (i = 0; i < PROP_COMPAT_NUM; i++)
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kfree(compat_strs[i]);
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return ret;
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}
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int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs,
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struct device_node *np)
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{
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int ret;
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/*
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* The added properties will be released when the
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* changeset is destroyed.
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*/
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if (pci_is_bridge(pdev)) {
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ret = of_changeset_add_prop_string(ocs, np, "device_type",
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"pci");
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if (ret)
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return ret;
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ret = of_pci_prop_bus_range(pdev, ocs, np);
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if (ret)
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return ret;
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ret = of_pci_prop_intr_map(pdev, ocs, np);
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if (ret)
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return ret;
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}
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ret = of_pci_prop_ranges(pdev, ocs, np);
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if (ret)
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return ret;
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ret = of_changeset_add_prop_u32(ocs, np, "#address-cells",
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OF_PCI_ADDRESS_CELLS);
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if (ret)
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return ret;
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ret = of_changeset_add_prop_u32(ocs, np, "#size-cells",
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OF_PCI_SIZE_CELLS);
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if (ret)
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return ret;
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ret = of_pci_prop_reg(pdev, ocs, np);
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if (ret)
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return ret;
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ret = of_pci_prop_compatible(pdev, ocs, np);
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if (ret)
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return ret;
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ret = of_pci_prop_interrupts(pdev, ocs, np);
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if (ret)
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return ret;
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return 0;
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}
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