Chris Wilson e4fc69f24b drm/i915/hsw: Flush RING_IMR changes before changing the global GT IMR (vecs) ... Haswell also requires the RING_IMR flush for its unique vebox setup to avoid losing interrupts, as per 476af9c260 ("drm/i915/gen6: Flush RING_IMR changes before changing the global GT IMR"): On Baytail, notably, we can still detect missed interrupt syndrome (where we never spot a completed request). In this case, it can be alleviated by always keeping the interrupt unmasked, implying that the interrupt is being lost in the window after modifying the IMR. (This is the reason we still have the posting reads on enable_irq, if we remove them we miss interrupts!) Having narrowed the issue down to the IMR, rather than keeping it always enabled, applying the usual posting read/flush of the RING_IMR before unmasking the GT IMR also seems to prevent the missed interrupt. So be it. References: 476af9c260 ("drm/i915/gen6: Flush RING_IMR changes before changing the global GT IMR") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190105115647.4970-1-chris@chris-wilson.co.uk		2019-01-07 11:32:29 +00:00
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drm	drm/i915/hsw: Flush RING_IMR changes before changing the global GT IMR (vecs)	2019-01-07 11:32:29 +00:00
host1x
ipu-v3
vga	drm-misc-next for v4.21, part 1:	2018-11-19 10:40:33 +10:00
Makefile