linux/arch/riscv/kernel
Yash Shah e0d17c842c
RISC-V: Don't allow write+exec only page mapping request in mmap
As per the table 4.4 of version "20190608-Priv-MSU-Ratified" of the
RISC-V instruction set manual[0], the PTE permission bit combination of
"write+exec only" is reserved for future use. Hence, don't allow such
mapping request in mmap call.

An issue is been reported by David Abdurachmanov, that while running
stress-ng with "sysbadaddr" argument, RCU stalls are observed on RISC-V
specific kernel.

This issue arises when the stress-sysbadaddr request for pages with
"write+exec only" permission bits and then passes the address obtain
from this mmap call to various system call. For the riscv kernel, the
mmap call should fail for this particular combination of permission bits
since it's not valid.

[0]: http://dabbelt.com/~palmer/keep/riscv-isa-manual/riscv-privileged-20190608-1.pdf

Signed-off-by: Yash Shah <yash.shah@sifive.com>
Reported-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
[Palmer: Refer to the latest ISA specification at the only link I could
find, and update the terminology.]
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-06-18 17:28:53 -07:00
..
vdso riscv: use vDSO common flow to reduce the latency of the time-related functions 2020-06-10 19:47:16 -07:00
.gitignore .gitignore: add SPDX License Identifier 2020-03-25 11:50:48 +01:00
asm-offsets.c riscv: abstract out CSR names for supervisor vs machine mode 2019-11-05 09:20:42 -08:00
cacheinfo.c riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structure 2020-05-20 15:05:05 -07:00
clint.c riscv: provide native clint access for M-mode 2019-11-17 15:17:39 -08:00
cpu-hotplug.c RISC-V: Support cpu hotplug 2020-03-31 11:28:30 -07:00
cpu.c RISC-V: Rename and move plic_find_hart_id() to arch directory 2020-06-09 19:11:20 -07:00
cpu_ops.c riscv: force __cpu_up_ variables to put in data section 2020-05-04 15:03:25 -07:00
cpu_ops_sbi.c RISC-V: Support cpu hotplug 2020-03-31 11:28:30 -07:00
cpu_ops_spinwait.c RISC-V: Add cpu_ops and modify default booting method 2020-03-31 11:25:56 -07:00
cpufeature.c RISC-V: Add bitmap reprensenting ISA features common across CPUs 2020-05-04 14:08:59 -07:00
entry.S RISC-V: Remove do_IRQ() function 2020-06-09 19:11:24 -07:00
fpu.S riscv: abstract out CSR names for supervisor vs machine mode 2019-11-05 09:20:42 -08:00
ftrace.c riscv: Use text_mutex instead of patch_lock 2020-05-18 11:38:16 -07:00
head.h riscv: add prototypes for assembly language functions from head.S 2019-10-28 00:46:00 -07:00
head.S RISC-V: Skip setting up PMPs on traps 2020-05-18 11:38:08 -07:00
irq.c RISC-V: Remove do_IRQ() function 2020-06-09 19:11:24 -07:00
kgdb.c riscv: Add SW single-step support for KDB 2020-05-18 11:38:12 -07:00
Makefile riscv: Add KGDB support 2020-05-18 11:38:10 -07:00
mcount-dyn.S riscv/ftrace: Add DYNAMIC_FTRACE_WITH_REGS support 2018-04-02 19:59:13 -07:00
mcount.S RISC-V: remove the unused return_to_handler export 2018-10-22 17:38:12 -07:00
module-sections.c riscv: add missing header file includes 2019-10-28 00:46:01 -07:00
module.c mm: introduce include/linux/pgtable.h 2020-06-09 09:39:13 -07:00
module.lds RISC-V: Add section of GOT.PLT for kernel module 2018-04-02 20:00:54 -07:00
patch.c riscv: fix build warning of missing prototypes 2020-06-09 19:11:27 -07:00
perf_callchain.c riscv: abstract out CSR names for supervisor vs machine mode 2019-11-05 09:20:42 -08:00
perf_event.c riscv: perf_event: Make some funciton static 2020-05-11 13:48:19 -07:00
perf_regs.c riscv: Add support for perf registers sampling 2019-09-05 00:48:58 -07:00
process.c RISC-V: gp_in_global needs register keyword 2020-05-21 13:28:26 -07:00
ptrace.c riscv: fix seccomp reject syscall code path 2020-03-05 13:58:15 -08:00
reset.c riscv: cleanup the default power off implementation 2019-11-13 13:22:52 -08:00
riscv_ksyms.c riscv: Add KASAN support 2020-01-22 13:09:58 -08:00
sbi.c riscv: sbi: Fix undefined reference to sbi_shutdown 2020-04-21 16:15:09 -07:00
setup.c mm: don't include asm/pgtable.h if linux/mm.h is already included 2020-06-09 09:39:13 -07:00
signal.c riscv: add nommu support 2019-11-17 15:17:39 -08:00
smp.c RISC-V: self-contained IPI handling routine 2020-06-09 19:11:19 -07:00
smpboot.c RISC-V: Add supported for ordered booting method using HSM 2020-03-31 11:27:50 -07:00
soc.c mm: introduce include/linux/pgtable.h 2020-06-09 09:39:13 -07:00
stacktrace.c kernel: rename show_stack_loglvl() => show_stack() 2020-06-09 09:39:13 -07:00
sys_riscv.c RISC-V: Don't allow write+exec only page mapping request in mmap 2020-06-18 17:28:53 -07:00
syscall_table.c riscv: add missing header file includes 2019-10-28 00:46:01 -07:00
time.c riscv: use vDSO common flow to reduce the latency of the time-related functions 2020-06-10 19:47:16 -07:00
traps.c irqchip: RISC-V per-HART local interrupt controller driver 2020-06-09 19:11:21 -07:00
traps_misaligned.c riscv: Unaligned load/store handling for M_MODE 2020-04-03 10:45:33 -07:00
vdso.c RISC-V Patches for the 5.8 Merge Window, Part 2 2020-06-11 12:55:20 -07:00
vmlinux.lds.S riscv: Allow device trees to be built into the kernel 2020-05-18 11:38:05 -07:00