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linux/drivers/gpu/drm/msm/dsi/phy
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Hai Li e01b1bfd88 drm/msm/dsi: Updata LNn_CFG4 register settings for 28nm PHY 
The current settings for 28nm PHY data lane CFG4 registers do
not work with certain panels. This change is to modify them to
hw recommended values.

Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-10-22 15:39:54 -04:00
..
dsi_phy.c drm: msm: dsi: Don't attempt changing voltage of switches 2015-10-22 15:39:53 -04:00
dsi_phy.h
dsi_phy_20nm.c
dsi_phy_28nm.c drm/msm/dsi: Updata LNn_CFG4 register settings for 28nm PHY 2015-10-22 15:39:54 -04:00