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d936a7e708
Instead of flushing cache per update_mmu_cache() called, we use flush_dcache_page to reduce the frequency of flashing the cache. As abiv2 cpus are all PIPT for icache & dcache, we needn't handle dcache aliasing problem. But their icache can't snoop dcache, so we still need sync_icache_dcache in update_mmu_cache(). Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
30 lines
665 B
C
30 lines
665 B
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#include <linux/cache.h>
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#include <linux/highmem.h>
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#include <linux/mm.h>
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#include <asm/cache.h>
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void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
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pte_t *pte)
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{
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unsigned long addr;
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struct page *page;
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page = pfn_to_page(pte_pfn(*pte));
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if (page == ZERO_PAGE(0))
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return;
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if (test_and_set_bit(PG_dcache_clean, &page->flags))
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return;
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addr = (unsigned long) kmap_atomic(page);
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dcache_wb_range(addr, addr + PAGE_SIZE);
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if (vma->vm_flags & VM_EXEC)
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icache_inv_range(addr, addr + PAGE_SIZE);
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kunmap_atomic((void *) addr);
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}
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