linux/drivers/clk/meson
Martin Blumenstingl d6e81845b7 clk: meson: clk-pll: check if the clock is already enabled
Since commit 6f888e7bc7bd58 ("clk: meson: clk-pll: add enable bit") our
PLLs also support the "enable" bit. Currently meson_clk_pll_enable
unconditionally resets the PLL, enables it, takes it out of reset and
waits until it is locked.

This works fine for our current clock trees. However, there will be a
problem once we allow modifications to sys_pll on Meson8, Meson8b and
Meson8m2 (which will be required for CPU frequency scaling):
the CPU clock is derived from the sys_pll clock. Once clk_enable is
called on the CPU clock this will be propagated by the common clock
framework up until the sys_pll clock. If we reset the PLL
unconditionally in meson_clk_pll_enable the CPU will be stopped (on
Meson8, Meson8b and Meson8m2).
To prevent this we simply check if the PLL is already enabled and do
reset the PLL if it's already enabled and locked.

Now that we have a utility function to check whether the PLL is enabled
we can also pass that to our clk_ops to let the common clock framework
know about the status of the hardware clock.
For now this is of limited use since the only common clock framework's
internal "disabled unused clocks" mechanism checks for this. Everything
else still uses the ref-counting (internal to the common clock
framework) when clk_enable is called.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181115224048.13511-2-martin.blumenstingl@googlemail.com
2018-11-23 15:11:57 +01:00
..
axg-aoclk.c clk: meson-axg: Add AO Clock and Reset controller driver 2018-05-15 14:19:43 +02:00
axg-aoclk.h clk: meson-axg: Add AO Clock and Reset controller driver 2018-05-15 14:19:43 +02:00
axg-audio.c clk: meson: axg: round audio system master clocks down 2018-09-26 12:02:00 +02:00
axg-audio.h clk: meson: axg: add the audio clock controller driver 2018-07-09 13:48:26 +02:00
axg.c clk: meson-axg: pcie: drop the mpll3 clock parent 2018-09-26 12:02:00 +02:00
axg.h clk: meson: clk-pll: remove od parameters 2018-09-26 12:01:57 +02:00
clk-mpll.c clk: meson: mpll: add round closest support 2018-05-21 11:31:29 +02:00
clk-phase.c clk: meson: add clk-phase clock driver 2018-07-09 13:47:22 +02:00
clk-pll.c clk: meson: clk-pll: check if the clock is already enabled 2018-11-23 15:11:57 +01:00
clk-regmap.c This time we have a good set of changes to the core framework that do some 2018-06-09 12:06:24 -07:00
clk-regmap.h clk: meson: use SPDX license identifiers consistently 2018-05-18 12:08:29 +02:00
clk-triphase.c clk: meson: add triple phase clock driver 2018-07-09 13:47:22 +02:00
clkc-audio.h clk: meson: add axg audio sclk divider driver 2018-07-09 13:48:25 +02:00
clkc.h clk: meson: Add vid_pll divider driver 2018-11-23 15:11:56 +01:00
gxbb-aoclk-32k.c clk: meson: use SPDX license identifiers consistently 2018-05-18 12:08:29 +02:00
gxbb-aoclk.c clk: meson: use SPDX license identifiers consistently 2018-05-18 12:08:29 +02:00
gxbb-aoclk.h This time we have a good set of changes to the core framework that do some 2018-06-09 12:06:24 -07:00
gxbb.c clk: meson-gxbb: Add video clocks 2018-11-23 15:11:56 +01:00
gxbb.h dt-bindings: clk: meson-gxbb: Add Video clock bindings 2018-11-23 15:11:56 +01:00
Kconfig clk: meson: axg: add the audio clock controller driver 2018-07-09 13:48:26 +02:00
Makefile clk: meson: Add vid_pll divider driver 2018-11-23 15:11:56 +01:00
meson-aoclk.c clk: meson: aoclk: refactor common code into dedicated file 2018-05-15 14:19:42 +02:00
meson-aoclk.h clk: meson: aoclk: refactor common code into dedicated file 2018-05-15 14:19:42 +02:00
meson8b.c clk: meson: meson8b: fix the width of the cpu_scale_div clock 2018-11-23 15:11:57 +01:00
meson8b.h clk: meson: clk-pll: remove od parameters 2018-09-26 12:01:57 +02:00
sclk-div.c clk: meson: add axg audio sclk divider driver 2018-07-09 13:48:25 +02:00
vid-pll-div.c clk: meson: Add vid_pll divider driver 2018-11-23 15:11:56 +01:00