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d992e52d7e
The GPIO configuration differs for the spi0 clk, cs, miso, mosi pins.
Therefore, split the spi0 pin group and document each pin function.
Fixes: b88752d313 ("dt-bindings: pinctrl: qcom: add IPQ5424 pinctrl")
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Link: https://lore.kernel.org/20241217091308.3253897-2-quic_mmanikan@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
114 lines
3.4 KiB
YAML
114 lines
3.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5424-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm IPQ5424 TLMM pin controller
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm IPQ5424 SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,ipq5424-tlmm
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 25
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gpio-line-names:
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maxItems: 50
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-ipq5424-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-ipq5424-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-ipq5424-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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pattern: "^gpio([0-9]|[1-4][0-9])$"
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minItems: 1
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maxItems: 50
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
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atest_tic, audio_pri, audio_pri0, audio_pri1, audio_sec,
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audio_sec0, audio_sec1, core_voltage, cri_trng0, cri_trng1,
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cri_trng2, cri_trng3, cxc_clk, cxc_data, dbg_out, gcc_plltest,
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gcc_tlmm, gpio, i2c0_scl, i2c0_sda, i2c1_scl, i2c1_sda, i2c11,
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mac0, mac1, mdc_mst, mdc_slv, mdio_mst, mdio_slv, pcie0_clk,
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pcie0_wake, pcie1_clk, pcie1_wake, pcie2_clk, pcie2_wake,
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pcie3_clk, pcie3_wake, pll_test, prng_rosc0, prng_rosc1,
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prng_rosc2, prng_rosc3, PTA0_0, PTA0_1, PTA0_2, PTA10, PTA11,
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pwm0, pwm1, pwm2, qdss_cti_trig_in_a0, qdss_cti_trig_out_a0,
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qdss_cti_trig_in_a1, qdss_cti_trig_out_a1, qdss_cti_trig_in_b0,
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qdss_cti_trig_out_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_b1,
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qdss_traceclk_a, qdss_tracectl_a, qdss_tracedata_a, qspi_clk,
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qspi_cs, qspi_data, resout, rx0, rx1, rx2, sdc_clk, sdc_cmd,
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sdc_data, spi0_cs, spi0_clk, spi0_miso, spi0_mosi, spi1, spi10,
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spi11, tsens_max, uart0, uart1, wci_txd, wci_rxd, wsi_clk, wsi_data ]
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required:
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- pins
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq5424-tlmm";
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reg = <0x01000000 0x300000>;
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gpio-controller;
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#gpio-cells = <0x2>;
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gpio-ranges = <&tlmm 0 0 50>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <0x2>;
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uart1_pins: uart1-state {
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pins = "gpio43", "gpio44";
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function = "uart1";
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drive-strength = <8>;
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bias-pull-up;
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};
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};
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