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d2d4f51d5a
Currently PSR flush is triggered from CRTC's .atomic_begin() callback, which is executed after modeset disables and enables and before plane updates are committed. Since PSR flush and re-enable can be triggered asynchronously by external sources (input event, delayed work), it can race with hardware programming done in the aforementioned stages. This patch blocks the PSR completely before hardware programming part begins and unblock after it ends. This relies on reference counted PSR disable introduced with previous patch. Cc: Kristian H. Kristensen <hoegsberg@chromium.org> Signed-off-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Escande <thierry.escande@collabora.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180423105003.9004-27-enric.balletbo@collabora.com |
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| .. | ||
| analogix_dp-rockchip.c | ||
| cdn-dp-core.c | ||
| cdn-dp-core.h | ||
| cdn-dp-reg.c | ||
| cdn-dp-reg.h | ||
| dw-mipi-dsi.c | ||
| dw_hdmi-rockchip.c | ||
| inno_hdmi.c | ||
| inno_hdmi.h | ||
| Kconfig | ||
| Makefile | ||
| rockchip_drm_drv.c | ||
| rockchip_drm_drv.h | ||
| rockchip_drm_fb.c | ||
| rockchip_drm_fb.h | ||
| rockchip_drm_fbdev.c | ||
| rockchip_drm_fbdev.h | ||
| rockchip_drm_gem.c | ||
| rockchip_drm_gem.h | ||
| rockchip_drm_psr.c | ||
| rockchip_drm_psr.h | ||
| rockchip_drm_vop.c | ||
| rockchip_drm_vop.h | ||
| rockchip_lvds.c | ||
| rockchip_lvds.h | ||
| rockchip_vop_reg.c | ||
| rockchip_vop_reg.h | ||