Chen-Yu Tsai cf9e6d5dbd media: sun4i-csi: Fix data sampling polarity handling ... The CLK_POL field specifies whether data is sampled on the falling or rising edge of PCLK, not whether the data lines are active high or low. Evidence of this can be found in the timing diagram labeled "horizontal size setting and pixel clock timing". Fix the setting by checking the correct flag, V4L2_MBUS_PCLK_SAMPLE_RISING. While at it, reorder the three polarity flag checks so HSYNC and VSYNC are grouped together. Fixes: 577bbf23b7 ("media: sunxi: Add A10 CSI driver") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>		2020-01-04 08:17:14 +01:00
..
sun4i-csi	media: sun4i-csi: Fix data sampling polarity handling	2020-01-04 08:17:14 +01:00
sun6i-csi	media: Remove dev_err() usage after platform_get_irq()	2019-08-07 17:08:33 -03:00
sun8i-di	media: sun8i: Remove redundant dev_err call in deinterlace_probe()	2019-12-16 10:20:10 +01:00
Kconfig	media: sunxi: Add A10 CSI driver	2019-08-23 07:31:35 -03:00
Makefile	media: sun4i: Add H3 deinterlace driver	2019-10-24 19:07:59 -03:00