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linux/drivers/gpu/drm/amd/include/asic_reg/gc
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Dennis Li ca3f422f53 drm/amd/include: add bitfield define for EDC registers 
Add EDC registers to support VEGA20 RAS

Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-31 14:50:47 -05:00
..
gc_9_0_default.h
gc_9_0_offset.h drm/amdgpu: add EDC counter register 2019-05-24 12:20:50 -05:00
gc_9_0_sh_mask.h drm/amd/include: add bitfield define for EDC registers 2019-07-31 14:50:47 -05:00
gc_9_1_offset.h
gc_9_1_sh_mask.h
gc_9_2_1_offset.h
gc_9_2_1_sh_mask.h drm/amd/include: update the bitfield define for PF_MAX_REGION 2018-09-10 22:45:51 -05:00
gc_10_1_0_default.h drm/amdgpu: add GC 10.1 register headers (v4) 2019-06-20 15:54:35 -05:00
gc_10_1_0_offset.h drm/amdgpu: add GC 10.1 register headers (v4) 2019-06-20 15:54:35 -05:00
gc_10_1_0_sh_mask.h drm/amdgpu: add GC 10.1 register headers (v4) 2019-06-20 15:54:35 -05:00