mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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-----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEV76QKkVc4xCGURexaDWVMHDJkrAFAmgebIwACgkQaDWVMHDJ krCGSA/+I+W/uqiz58Z2Zu4RrXMYFfKJxacF7My9wnOyRxaJduS3qrz1E5wHqBId f6M8wDx9nS24UxDkBbi84NdtlG1zj8nV8djtszGKVeqHG2DcQMMOXBKZSjOmTo2b GIZ3a3xEqXaFfnGQxXSZrvtHIwCmv10H2oyGHu0vBp/SJuWXNg72oivOGhbm0uWs 0/bdIK8+1sW7OAmhhKdvMVpmzL8TQJnkUHSkQilPB2Tsf9wWDfeY7kDkK5YwQpk2 ZK+hrmwCFXQZELY65F2+y/cFim/F38HiqVdvIkV1wFSVqVVE9hEKJ4BDZl1fXZKB p4qpDFgxO27E/eMo9IZfxRH4TdSoK6YLWo9FGWHKBPnciJfAeO9EP/AwAIhEQRdx YZlN9sGS6ja7O1Eh423BBw6cFj6ta0ck2T1PoYk32FXc6sgqCphsfvBD3+tJxz8/ xoZ3BzoErdPqSXbH5cSI972kQW0JLESiMTZa827qnJtT672t6uBcsnnmR0ZbJH1f TJCC9qgwpBiEkiGW3gwv00SC7CkXo3o0FJw0pa3MkKHGd7csxBtGBHI1b6Jj+oB0 yWf1HxSqwrq2Yek8R7lWd4jIxyWfKriEMTu7xCMUUFlprKmR2RufsADvqclNyedQ sGBCc4eu1cpZp2no/IFm+IvkuzUHnkS/WNL1LbZ9YI8h8unjZHE= =UVgZ -----END PGP SIGNATURE----- Merge tag 'its-for-linus-20250509' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 ITS mitigation from Dave Hansen: "Mitigate Indirect Target Selection (ITS) issue. I'd describe this one as a good old CPU bug where the behavior is _obviously_ wrong, but since it just results in bad predictions it wasn't wrong enough to notice. Well, the researchers noticed and also realized that thus bug undermined a bunch of existing indirect branch mitigations. Thus the unusually wide impact on this one. Details: ITS is a bug in some Intel CPUs that affects indirect branches including RETs in the first half of a cacheline. Due to ITS such branches may get wrongly predicted to a target of (direct or indirect) branch that is located in the second half of a cacheline. Researchers at VUSec found this behavior and reported to Intel. Affected processors: - Cascade Lake, Cooper Lake, Whiskey Lake V, Coffee Lake R, Comet Lake, Ice Lake, Tiger Lake and Rocket Lake. Scope of impact: - Guest/host isolation: When eIBRS is used for guest/host isolation, the indirect branches in the VMM may still be predicted with targets corresponding to direct branches in the guest. - Intra-mode using cBPF: cBPF can be used to poison the branch history to exploit ITS. Realigning the indirect branches and RETs mitigates this attack vector. - User/kernel: With eIBRS enabled user/kernel isolation is *not* impacted by ITS. - Indirect Branch Prediction Barrier (IBPB): Due to this bug indirect branches may be predicted with targets corresponding to direct branches which were executed prior to IBPB. This will be fixed in the microcode. Mitigation: As indirect branches in the first half of cacheline are affected, the mitigation is to replace those indirect branches with a call to thunk that is aligned to the second half of the cacheline. RETs that take prediction from RSB are not affected, but they may be affected by RSB-underflow condition. So, RETs in the first half of cacheline are also patched to a return thunk that executes the RET aligned to second half of cacheline" * tag 'its-for-linus-20250509' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: selftest/x86/bugs: Add selftests for ITS x86/its: FineIBT-paranoid vs ITS x86/its: Use dynamic thunks for indirect branches x86/ibt: Keep IBT disabled during alternative patching mm/execmem: Unify early execmem_cache behaviour x86/its: Align RETs in BHB clear sequence to avoid thunking x86/its: Add support for RSB stuffing mitigation x86/its: Add "vmexit" option to skip mitigation on some CPUs x86/its: Enable Indirect Target Selection mitigation x86/its: Add support for ITS-safe return thunk x86/its: Add support for ITS-safe indirect thunk x86/its: Enumerate Indirect Target Selection (ITS) bug Documentation: x86/bugs/its: Add ITS documentation
533 lines
14 KiB
ArmAsm
533 lines
14 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* ld script for the x86 kernel
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*
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* Historic 32-bit version written by Martin Mares <mj@atrey.karlin.mff.cuni.cz>
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*
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* Modernisation, unification and other changes and fixes:
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* Copyright (C) 2007-2009 Sam Ravnborg <sam@ravnborg.org>
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*
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*
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* Don't define absolute symbols until and unless you know that symbol
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* value is should remain constant even if kernel image is relocated
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* at run time. Absolute symbols are not relocated. If symbol value should
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* change if kernel is relocated, make the symbol section relative and
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* put it inside the section definition.
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*/
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#define LOAD_OFFSET __START_KERNEL_map
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#define RUNTIME_DISCARD_EXIT
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#define EMITS_PT_NOTE
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#define RO_EXCEPTION_TABLE_ALIGN 16
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#include <asm-generic/vmlinux.lds.h>
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#include <asm/asm-offsets.h>
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#include <asm/thread_info.h>
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#include <asm/page_types.h>
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#include <asm/orc_lookup.h>
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#include <asm/cache.h>
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#include <asm/boot.h>
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#include <asm/kexec.h>
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#undef i386 /* in case the preprocessor is a 32bit one */
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OUTPUT_FORMAT(CONFIG_OUTPUT_FORMAT)
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#ifdef CONFIG_X86_32
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OUTPUT_ARCH(i386)
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ENTRY(phys_startup_32)
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#else
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OUTPUT_ARCH(i386:x86-64)
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ENTRY(phys_startup_64)
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#endif
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jiffies = jiffies_64;
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const_current_task = current_task;
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const_cpu_current_top_of_stack = cpu_current_top_of_stack;
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#if defined(CONFIG_X86_64)
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/*
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* On 64-bit, align RODATA to 2MB so we retain large page mappings for
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* boundaries spanning kernel text, rodata and data sections.
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*
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* However, kernel identity mappings will have different RWX permissions
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* to the pages mapping to text and to the pages padding (which are freed) the
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* text section. Hence kernel identity mappings will be broken to smaller
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* pages. For 64-bit, kernel text and kernel identity mappings are different,
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* so we can enable protection checks as well as retain 2MB large page
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* mappings for kernel text.
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*/
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#define X86_ALIGN_RODATA_BEGIN . = ALIGN(HPAGE_SIZE);
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#define X86_ALIGN_RODATA_END \
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. = ALIGN(HPAGE_SIZE); \
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__end_rodata_hpage_align = .; \
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__end_rodata_aligned = .;
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#define ALIGN_ENTRY_TEXT_BEGIN . = ALIGN(PMD_SIZE);
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#define ALIGN_ENTRY_TEXT_END . = ALIGN(PMD_SIZE);
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/*
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* This section contains data which will be mapped as decrypted. Memory
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* encryption operates on a page basis. Make this section PMD-aligned
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* to avoid splitting the pages while mapping the section early.
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*
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* Note: We use a separate section so that only this section gets
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* decrypted to avoid exposing more than we wish.
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*/
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#define BSS_DECRYPTED \
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. = ALIGN(PMD_SIZE); \
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__start_bss_decrypted = .; \
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*(.bss..decrypted); \
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. = ALIGN(PAGE_SIZE); \
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__start_bss_decrypted_unused = .; \
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. = ALIGN(PMD_SIZE); \
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__end_bss_decrypted = .; \
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#else
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#define X86_ALIGN_RODATA_BEGIN
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#define X86_ALIGN_RODATA_END \
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. = ALIGN(PAGE_SIZE); \
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__end_rodata_aligned = .;
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#define ALIGN_ENTRY_TEXT_BEGIN
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#define ALIGN_ENTRY_TEXT_END
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#define BSS_DECRYPTED
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#endif
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#if defined(CONFIG_X86_64) && defined(CONFIG_KEXEC_CORE)
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#define KEXEC_RELOCATE_KERNEL \
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. = ALIGN(0x100); \
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__relocate_kernel_start = .; \
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*(.text..relocate_kernel); \
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*(.data..relocate_kernel); \
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__relocate_kernel_end = .;
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ASSERT(__relocate_kernel_end - __relocate_kernel_start <= KEXEC_CONTROL_CODE_MAX_SIZE,
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"relocate_kernel code too large!")
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#else
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#define KEXEC_RELOCATE_KERNEL
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#endif
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PHDRS {
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text PT_LOAD FLAGS(5); /* R_E */
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data PT_LOAD FLAGS(6); /* RW_ */
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note PT_NOTE FLAGS(0); /* ___ */
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}
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SECTIONS
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{
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. = __START_KERNEL;
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#ifdef CONFIG_X86_32
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phys_startup_32 = ABSOLUTE(startup_32 - LOAD_OFFSET);
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#else
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phys_startup_64 = ABSOLUTE(startup_64 - LOAD_OFFSET);
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#endif
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/* Text and read-only data */
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.text : AT(ADDR(.text) - LOAD_OFFSET) {
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_text = .;
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_stext = .;
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ALIGN_ENTRY_TEXT_BEGIN
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*(.text..__x86.rethunk_untrain)
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ENTRY_TEXT
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#ifdef CONFIG_MITIGATION_SRSO
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/*
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* See the comment above srso_alias_untrain_ret()'s
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* definition.
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*/
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. = srso_alias_untrain_ret | (1 << 2) | (1 << 8) | (1 << 14) | (1 << 20);
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*(.text..__x86.rethunk_safe)
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#endif
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ALIGN_ENTRY_TEXT_END
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TEXT_TEXT
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SCHED_TEXT
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LOCK_TEXT
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KPROBES_TEXT
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SOFTIRQENTRY_TEXT
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#ifdef CONFIG_MITIGATION_RETPOLINE
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*(.text..__x86.indirect_thunk)
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*(.text..__x86.return_thunk)
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#endif
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STATIC_CALL_TEXT
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*(.gnu.warning)
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} :text = 0xcccccccc
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/* bootstrapping code */
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.head.text : AT(ADDR(.head.text) - LOAD_OFFSET) {
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HEAD_TEXT
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} :text = 0xcccccccc
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/* End of text section, which should occupy whole number of pages */
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_etext = .;
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. = ALIGN(PAGE_SIZE);
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X86_ALIGN_RODATA_BEGIN
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RO_DATA(PAGE_SIZE)
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X86_ALIGN_RODATA_END
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/* Data */
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.data : AT(ADDR(.data) - LOAD_OFFSET) {
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/* Start of data section */
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_sdata = .;
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/* init_task */
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INIT_TASK_DATA(THREAD_SIZE)
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/* equivalent to task_pt_regs(&init_task) */
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__top_init_kernel_stack = __end_init_stack - TOP_OF_KERNEL_STACK_PADDING - PTREGS_SIZE;
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#ifdef CONFIG_X86_32
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/* 32 bit has nosave before _edata */
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NOSAVE_DATA
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#endif
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PAGE_ALIGNED_DATA(PAGE_SIZE)
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CACHE_HOT_DATA(L1_CACHE_BYTES)
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CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES)
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DATA_DATA
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CONSTRUCTORS
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KEXEC_RELOCATE_KERNEL
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/* rarely changed data like cpu maps */
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READ_MOSTLY_DATA(INTERNODE_CACHE_BYTES)
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/* End of data section */
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_edata = .;
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} :data
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BUG_TABLE
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ORC_UNWIND_TABLE
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/* Init code and data - will be freed after init */
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. = ALIGN(PAGE_SIZE);
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.init.begin : AT(ADDR(.init.begin) - LOAD_OFFSET) {
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__init_begin = .; /* paired with __init_end */
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}
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INIT_TEXT_SECTION(PAGE_SIZE)
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/*
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* Section for code used exclusively before alternatives are run. All
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* references to such code must be patched out by alternatives, normally
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* by using X86_FEATURE_ALWAYS CPU feature bit.
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*
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* See static_cpu_has() for an example.
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*/
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.altinstr_aux : AT(ADDR(.altinstr_aux) - LOAD_OFFSET) {
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*(.altinstr_aux)
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}
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INIT_DATA_SECTION(16)
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.x86_cpu_dev.init : AT(ADDR(.x86_cpu_dev.init) - LOAD_OFFSET) {
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__x86_cpu_dev_start = .;
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*(.x86_cpu_dev.init)
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__x86_cpu_dev_end = .;
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}
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#ifdef CONFIG_X86_INTEL_MID
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.x86_intel_mid_dev.init : AT(ADDR(.x86_intel_mid_dev.init) - \
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LOAD_OFFSET) {
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__x86_intel_mid_dev_start = .;
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*(.x86_intel_mid_dev.init)
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__x86_intel_mid_dev_end = .;
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}
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#endif
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#ifdef CONFIG_MITIGATION_RETPOLINE
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/*
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* List of instructions that call/jmp/jcc to retpoline thunks
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* __x86_indirect_thunk_*(). These instructions can be patched along
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* with alternatives, after which the section can be freed.
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*/
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. = ALIGN(8);
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.retpoline_sites : AT(ADDR(.retpoline_sites) - LOAD_OFFSET) {
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__retpoline_sites = .;
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*(.retpoline_sites)
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__retpoline_sites_end = .;
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}
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. = ALIGN(8);
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.return_sites : AT(ADDR(.return_sites) - LOAD_OFFSET) {
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__return_sites = .;
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*(.return_sites)
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__return_sites_end = .;
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}
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. = ALIGN(8);
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.call_sites : AT(ADDR(.call_sites) - LOAD_OFFSET) {
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__call_sites = .;
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*(.call_sites)
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__call_sites_end = .;
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}
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#endif
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#ifdef CONFIG_X86_KERNEL_IBT
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. = ALIGN(8);
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.ibt_endbr_seal : AT(ADDR(.ibt_endbr_seal) - LOAD_OFFSET) {
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__ibt_endbr_seal = .;
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*(.ibt_endbr_seal)
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__ibt_endbr_seal_end = .;
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}
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#endif
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#ifdef CONFIG_FINEIBT
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. = ALIGN(8);
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.cfi_sites : AT(ADDR(.cfi_sites) - LOAD_OFFSET) {
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__cfi_sites = .;
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*(.cfi_sites)
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__cfi_sites_end = .;
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}
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#endif
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/*
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* struct alt_inst entries. From the header (alternative.h):
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* "Alternative instructions for different CPU types or capabilities"
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* Think locking instructions on spinlocks.
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*/
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. = ALIGN(8);
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.altinstructions : AT(ADDR(.altinstructions) - LOAD_OFFSET) {
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__alt_instructions = .;
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*(.altinstructions)
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__alt_instructions_end = .;
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}
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/*
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* And here are the replacement instructions. The linker sticks
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* them as binary blobs. The .altinstructions has enough data to
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* get the address and the length of them to patch the kernel safely.
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*/
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.altinstr_replacement : AT(ADDR(.altinstr_replacement) - LOAD_OFFSET) {
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*(.altinstr_replacement)
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}
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. = ALIGN(8);
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.apicdrivers : AT(ADDR(.apicdrivers) - LOAD_OFFSET) {
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__apicdrivers = .;
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*(.apicdrivers);
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__apicdrivers_end = .;
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}
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. = ALIGN(8);
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/*
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* .exit.text is discarded at runtime, not link time, to deal with
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* references from .altinstructions
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*/
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.exit.text : AT(ADDR(.exit.text) - LOAD_OFFSET) {
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EXIT_TEXT
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}
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.exit.data : AT(ADDR(.exit.data) - LOAD_OFFSET) {
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EXIT_DATA
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}
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PERCPU_SECTION(L1_CACHE_BYTES)
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ASSERT(__per_cpu_hot_end - __per_cpu_hot_start <= 64, "percpu cache hot data too large")
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RUNTIME_CONST_VARIABLES
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RUNTIME_CONST(ptr, USER_PTR_MAX)
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. = ALIGN(PAGE_SIZE);
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/* freed after init ends here */
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.init.end : AT(ADDR(.init.end) - LOAD_OFFSET) {
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__init_end = .;
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}
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/*
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* smp_locks might be freed after init
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* start/end must be page aligned
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*/
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. = ALIGN(PAGE_SIZE);
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.smp_locks : AT(ADDR(.smp_locks) - LOAD_OFFSET) {
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__smp_locks = .;
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*(.smp_locks)
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. = ALIGN(PAGE_SIZE);
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__smp_locks_end = .;
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}
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#ifdef CONFIG_X86_64
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.data_nosave : AT(ADDR(.data_nosave) - LOAD_OFFSET) {
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NOSAVE_DATA
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}
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#endif
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/* BSS */
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. = ALIGN(PAGE_SIZE);
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.bss : AT(ADDR(.bss) - LOAD_OFFSET) {
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__bss_start = .;
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*(.bss..page_aligned)
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. = ALIGN(PAGE_SIZE);
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*(BSS_MAIN)
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BSS_DECRYPTED
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. = ALIGN(PAGE_SIZE);
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__bss_stop = .;
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}
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/*
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* The memory occupied from _text to here, __end_of_kernel_reserve, is
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* automatically reserved in setup_arch(). Anything after here must be
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* explicitly reserved using memblock_reserve() or it will be discarded
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* and treated as available memory.
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*/
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__end_of_kernel_reserve = .;
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. = ALIGN(PAGE_SIZE);
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.brk : AT(ADDR(.brk) - LOAD_OFFSET) {
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__brk_base = .;
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. += 64 * 1024; /* 64k alignment slop space */
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*(.bss..brk) /* areas brk users have reserved */
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__brk_limit = .;
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}
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. = ALIGN(PAGE_SIZE); /* keep VO_INIT_SIZE page aligned */
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_end = .;
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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/*
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* Early scratch/workarea section: Lives outside of the kernel proper
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* (_text - _end).
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*
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* Resides after _end because even though the .brk section is after
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* __end_of_kernel_reserve, the .brk section is later reserved as a
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* part of the kernel. Since it is located after __end_of_kernel_reserve
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* it will be discarded and become part of the available memory. As
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* such, it can only be used by very early boot code and must not be
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* needed afterwards.
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*
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* Currently used by SME for performing in-place encryption of the
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* kernel during boot. Resides on a 2MB boundary to simplify the
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* pagetable setup used for SME in-place encryption.
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*/
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. = ALIGN(HPAGE_SIZE);
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.init.scratch : AT(ADDR(.init.scratch) - LOAD_OFFSET) {
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__init_scratch_begin = .;
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*(.init.scratch)
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. = ALIGN(HPAGE_SIZE);
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__init_scratch_end = .;
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}
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#endif
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STABS_DEBUG
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DWARF_DEBUG
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#ifdef CONFIG_PROPELLER_CLANG
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.llvm_bb_addr_map : { *(.llvm_bb_addr_map) }
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#endif
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ELF_DETAILS
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DISCARDS
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/*
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* Make sure that the .got.plt is either completely empty or it
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* contains only the lazy dispatch entries.
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*/
|
|
.got.plt (INFO) : { *(.got.plt) }
|
|
ASSERT(SIZEOF(.got.plt) == 0 ||
|
|
#ifdef CONFIG_X86_64
|
|
SIZEOF(.got.plt) == 0x18,
|
|
#else
|
|
SIZEOF(.got.plt) == 0xc,
|
|
#endif
|
|
"Unexpected GOT/PLT entries detected!")
|
|
|
|
/*
|
|
* Sections that should stay zero sized, which is safer to
|
|
* explicitly check instead of blindly discarding.
|
|
*/
|
|
.got : {
|
|
*(.got) *(.igot.*)
|
|
}
|
|
ASSERT(SIZEOF(.got) == 0, "Unexpected GOT entries detected!")
|
|
|
|
.plt : {
|
|
*(.plt) *(.plt.*) *(.iplt)
|
|
}
|
|
ASSERT(SIZEOF(.plt) == 0, "Unexpected run-time procedure linkages detected!")
|
|
|
|
.rel.dyn : {
|
|
*(.rel.*) *(.rel_*)
|
|
}
|
|
ASSERT(SIZEOF(.rel.dyn) == 0, "Unexpected run-time relocations (.rel) detected!")
|
|
|
|
.rela.dyn : {
|
|
*(.rela.*) *(.rela_*)
|
|
}
|
|
ASSERT(SIZEOF(.rela.dyn) == 0, "Unexpected run-time relocations (.rela) detected!")
|
|
}
|
|
|
|
/*
|
|
* COMPILE_TEST kernels can be large - CONFIG_KASAN, for example, can cause
|
|
* this. Let's assume that nobody will be running a COMPILE_TEST kernel and
|
|
* let's assert that fuller build coverage is more valuable than being able to
|
|
* run a COMPILE_TEST kernel.
|
|
*/
|
|
#ifndef CONFIG_COMPILE_TEST
|
|
/*
|
|
* The ASSERT() sync to . is intentional, for binutils 2.14 compatibility:
|
|
*/
|
|
. = ASSERT((_end - LOAD_OFFSET <= KERNEL_IMAGE_SIZE),
|
|
"kernel image bigger than KERNEL_IMAGE_SIZE");
|
|
#endif
|
|
|
|
/* needed for Clang - see arch/x86/entry/entry.S */
|
|
PROVIDE(__ref_stack_chk_guard = __stack_chk_guard);
|
|
|
|
#ifdef CONFIG_X86_64
|
|
|
|
#ifdef CONFIG_MITIGATION_UNRET_ENTRY
|
|
. = ASSERT((retbleed_return_thunk & 0x3f) == 0, "retbleed_return_thunk not cacheline-aligned");
|
|
#endif
|
|
|
|
#ifdef CONFIG_MITIGATION_SRSO
|
|
. = ASSERT((srso_safe_ret & 0x3f) == 0, "srso_safe_ret not cacheline-aligned");
|
|
/*
|
|
* GNU ld cannot do XOR until 2.41.
|
|
* https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=f6f78318fca803c4907fb8d7f6ded8295f1947b1
|
|
*
|
|
* LLVM lld cannot do XOR until lld-17.
|
|
* https://github.com/llvm/llvm-project/commit/fae96104d4378166cbe5c875ef8ed808a356f3fb
|
|
*
|
|
* Instead do: (A | B) - (A & B) in order to compute the XOR
|
|
* of the two function addresses:
|
|
*/
|
|
. = ASSERT(((ABSOLUTE(srso_alias_untrain_ret) | srso_alias_safe_ret) -
|
|
(ABSOLUTE(srso_alias_untrain_ret) & srso_alias_safe_ret)) == ((1 << 2) | (1 << 8) | (1 << 14) | (1 << 20)),
|
|
"SRSO function pair won't alias");
|
|
#endif
|
|
|
|
#if defined(CONFIG_MITIGATION_ITS) && !defined(CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B)
|
|
. = ASSERT(__x86_indirect_its_thunk_rax & 0x20, "__x86_indirect_thunk_rax not in second half of cacheline");
|
|
. = ASSERT(((__x86_indirect_its_thunk_rcx - __x86_indirect_its_thunk_rax) % 64) == 0, "Indirect thunks are not cacheline apart");
|
|
. = ASSERT(__x86_indirect_its_thunk_array == __x86_indirect_its_thunk_rax, "Gap in ITS thunk array");
|
|
#endif
|
|
|
|
#if defined(CONFIG_MITIGATION_ITS) && !defined(CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B)
|
|
. = ASSERT(its_return_thunk & 0x20, "its_return_thunk not in second half of cacheline");
|
|
#endif
|
|
|
|
#endif /* CONFIG_X86_64 */
|
|
|
|
/*
|
|
* The symbols below are referenced using relative relocations in the
|
|
* respective ELF notes. This produces build time constants that the
|
|
* linker will never mark as relocatable. (Using just ABSOLUTE() is not
|
|
* sufficient for that).
|
|
*/
|
|
#ifdef CONFIG_XEN_PV
|
|
xen_elfnote_entry_value =
|
|
ABSOLUTE(xen_elfnote_entry) + ABSOLUTE(startup_xen);
|
|
#endif
|
|
#ifdef CONFIG_PVH
|
|
xen_elfnote_phys32_entry_value =
|
|
ABSOLUTE(xen_elfnote_phys32_entry) + ABSOLUTE(pvh_start_xen - LOAD_OFFSET);
|
|
#endif
|