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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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8c49678d84
The node name of Ethernet controller should be "ethernet" instead of
"asix" or "smsc" as required by Ethernet controller devicetree schema:
Documentation/devicetree/bindings/net/ethernet-controller.yaml
This patch can potentially affect boot loaders patching against full
node path instead of using device aliases.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
776 lines
19 KiB
Text
776 lines
19 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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#include "tegra20.dtsi"
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/*
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* Toradex Colibri T20 Module Device Tree
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* Compatible for Revisions Colibri T20 256MB V1.1B, V1.2A;
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* Colibri T20 256MB IT V1.2A; Colibri T20 512MB V1.1C, V1.2A;
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* Colibri T20 512MB IT V1.2A
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*/
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/ {
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memory@0 {
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/*
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* Set memory to 256 MB to be safe as this could be used on
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* 256 or 512 MB module. It is expected from bootloader
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* to fix this up for 512 MB version.
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*/
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reg = <0x00000000 0x10000000>;
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};
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host1x@50000000 {
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hdmi@54280000 {
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nvidia,ddc-i2c-bus = <&hdmi_ddc>;
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nvidia,hpd-gpio =
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<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
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pll-supply = <®_1v8_avdd_hdmi_pll>;
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vdd-supply = <®_3v3_avdd_hdmi>;
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};
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};
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pinmux@70000014 {
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinmux {
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/* Analogue Audio AC97 to WM9712 (On-module) */
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audio-refclk {
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nvidia,pins = "cdev1";
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nvidia,function = "plla_out";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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dap3 {
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nvidia,pins = "dap3";
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nvidia,function = "dap3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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/*
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* AC97_RESET, ULPI_RESET, AC97_INT aka WM9712 GENIRQ
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* (All on-module), SODIMM Pin 45 Wakeup
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*/
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gpio-uac {
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nvidia,pins = "uac";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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/*
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* Buffer Enables for nPWE and RDnWR (On-module,
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* see GPIO hogging further down below)
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*/
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gpio-pta {
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nvidia,pins = "pta";
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nvidia,function = "rsvd4";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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/*
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* CLK_32K_OUT, CORE_PWR_REQ, CPU_PWR_REQ, PWR_INT_N,
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* SYS_CLK_REQ (All on-module)
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*/
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pmc {
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nvidia,pins = "pmc";
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nvidia,function = "pwr_on";
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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/*
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* Colibri Address/Data Bus (GMI)
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* Note: spid and spie optionally used for SPI1
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*/
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gmi {
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nvidia,pins = "atc", "atd", "ate", "dap1",
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"dap2", "dap4", "gmd", "gpu",
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"irrx", "irtx", "spia", "spib",
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"spic", "spid", "spie", "uca",
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"ucb";
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nvidia,function = "gmi";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/* Further pins may be used as GPIOs */
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gmi-gpio1 {
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nvidia,pins = "lpw0", "lsc1", "lsck", "lsda";
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nvidia,function = "hdmi";
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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gmi-gpio2 {
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nvidia,pins = "lcsn", "ldc", "lm0", "lsdi";
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nvidia,function = "rsvd4";
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/* Colibri BL_ON */
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bl-on {
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nvidia,pins = "dta";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/* Colibri Backlight PWM<A>, PWM<B> */
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sdc {
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nvidia,pins = "sdc";
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nvidia,function = "pwm";
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/* Colibri DDC */
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ddc {
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nvidia,pins = "ddc";
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nvidia,function = "i2c2";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/*
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* Colibri EXT_IO*
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* Note: dtf optionally used for I2C3
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*/
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ext-io {
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nvidia,pins = "dtf", "spdi";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/*
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* Colibri Ethernet (On-module)
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* ULPI EHCI instance 1 USB2_DP/N -> AX88772B
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*/
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ulpi {
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nvidia,pins = "uaa", "uab", "uda";
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nvidia,function = "ulpi";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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ulpi-refclk {
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nvidia,pins = "cdev2";
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nvidia,function = "pllp_out4";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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/* Colibri HOTPLUG_DETECT (HDMI) */
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hotplug-detect {
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nvidia,pins = "hdint";
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nvidia,function = "hdmi";
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/* Colibri I2C */
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i2c {
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nvidia,pins = "rm";
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nvidia,function = "i2c1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/*
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* Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
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* today's display need DE, disable LCD_M1
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*/
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lm1 {
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nvidia,pins = "lm1";
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nvidia,function = "rsvd3";
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/* Colibri LCD (L_* resp. LDD<*>) */
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lcd {
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nvidia,pins = "ld0", "ld1", "ld2", "ld3",
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"ld4", "ld5", "ld6", "ld7",
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"ld8", "ld9", "ld10", "ld11",
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"ld12", "ld13", "ld14", "ld15",
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"ld16", "ld17", "lhs", "lsc0",
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"lspi", "lvs";
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nvidia,function = "displaya";
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/* Colibri LCD (Optional 24 BPP Support) */
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lcd-24 {
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nvidia,pins = "ldi", "lhp0", "lhp1", "lhp2",
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"lpp", "lvp1";
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nvidia,function = "displaya";
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/* Colibri MMC */
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mmc {
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nvidia,pins = "atb", "gma";
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nvidia,function = "sdio4";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/* Colibri MMCCD */
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mmccd {
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nvidia,pins = "gmb";
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nvidia,function = "gmi_int";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/* Colibri MMC (Optional 8-bit) */
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mmc-8bit {
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nvidia,pins = "gme";
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nvidia,function = "sdio4";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/*
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* Colibri Parallel Camera (Optional)
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* pins multiplexed with others and therefore disabled
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* Note: dta used for BL_ON by default
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*/
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cif-mclk {
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nvidia,pins = "csus";
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nvidia,function = "vi_sensor_clk";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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cif {
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nvidia,pins = "dtb", "dtc", "dtd";
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nvidia,function = "vi";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/* Colibri PWM<C>, PWM<D> */
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sdb_sdd {
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nvidia,pins = "sdb", "sdd";
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nvidia,function = "pwm";
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/* Colibri SSP */
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ssp {
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nvidia,pins = "slxa", "slxc", "slxd", "slxk";
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nvidia,function = "spi4";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/* Colibri UART-A */
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uart-a {
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nvidia,pins = "sdio1";
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nvidia,function = "uarta";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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uart-a-dsr {
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nvidia,pins = "lpw1";
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nvidia,function = "rsvd3";
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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uart-a-dcd {
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nvidia,pins = "lpw2";
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nvidia,function = "hdmi";
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/* Colibri UART-B */
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uart-b {
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nvidia,pins = "gmc";
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nvidia,function = "uartd";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/* Colibri UART-C */
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uart-c {
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nvidia,pins = "uad";
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nvidia,function = "irda";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/* Colibri USB_CDET */
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usb-cdet {
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nvidia,pins = "spdo";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/* Colibri USBH_OC */
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usbh-oc {
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nvidia,pins = "spih";
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nvidia,function = "spi2_alt";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/* Colibri USBH_PEN */
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usbh-pen {
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nvidia,pins = "spig";
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nvidia,function = "spi2_alt";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/* Colibri VGA not supported */
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vga {
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nvidia,pins = "crtp";
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nvidia,function = "crt";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/* I2C3 (Optional) */
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i2c3 {
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nvidia,pins = "dtf";
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nvidia,function = "i2c3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/* JTAG_RTCK */
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jtag-rtck {
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nvidia,pins = "gpu7";
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nvidia,function = "rtck";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/*
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* LAN_RESET, LAN_EXT_WAKEUP and LAN_PME
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* (All On-module)
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*/
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gpio-gpv {
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nvidia,pins = "gpv";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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/*
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* LAN_V_BUS, VDD_FAULT, BATT_FAULT, WM9712 PENDOWN
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* (All On-module); Colibri CAN_INT
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*/
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gpio-dte {
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nvidia,pins = "dte";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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/* NAND (On-module) */
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nand {
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nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
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"kbce", "kbcf";
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nvidia,function = "nand";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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/* Onewire (Optional) */
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owr {
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nvidia,pins = "owc";
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nvidia,function = "owr";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/* Power I2C (On-module) */
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i2cp {
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nvidia,pins = "i2cp";
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nvidia,function = "i2cp";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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/* RESET_OUT */
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reset-out {
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nvidia,pins = "ata";
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nvidia,function = "gmi";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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/*
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* SPI1 (Optional)
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* Note: spid and spie used for Colibri Address/Data
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* Bus (GMI)
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*/
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spi1 {
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nvidia,pins = "spid", "spie", "spif";
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nvidia,function = "spi1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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/*
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* THERMD_ALERT# (On-module), unlatched I2C address pin
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* of LM95245 temperature sensor therefore requires
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* disabling for now
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*/
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lvp0 {
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nvidia,pins = "lvp0";
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nvidia,function = "rsvd3";
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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};
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};
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tegra_ac97: ac97@70002000 {
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status = "okay";
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nvidia,codec-reset-gpio =
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<&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
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nvidia,codec-sync-gpio =
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<&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
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};
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serial@70006040 {
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compatible = "nvidia,tegra20-hsuart";
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/delete-property/ reg-shift;
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};
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serial@70006300 {
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compatible = "nvidia,tegra20-hsuart";
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/delete-property/ reg-shift;
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};
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nand-controller@70008000 {
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status = "okay";
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nand@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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nand-bus-width = <8>;
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nand-on-flash-bbt;
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nand-ecc-algo = "bch";
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nand-is-boot-medium;
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nand-ecc-maximize;
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wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
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};
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};
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/*
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* GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
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* board)
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*/
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i2c@7000c000 {
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clock-frequency = <400000>;
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};
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/* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */
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hdmi_ddc: i2c@7000c400 {
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clock-frequency = <10000>;
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};
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/* GEN2_I2C: unused */
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/* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */
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/* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */
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i2c@7000d000 {
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status = "okay";
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clock-frequency = <100000>;
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pmic@34 {
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compatible = "ti,tps6586x";
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reg = <0x34>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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ti,system-power-controller;
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#gpio-cells = <2>;
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gpio-controller;
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sys-supply = <®_module_3v3>;
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vin-sm0-supply = <®_3v3_vsys>;
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vin-sm1-supply = <®_3v3_vsys>;
|
|
vin-sm2-supply = <®_3v3_vsys>;
|
|
vinldo01-supply = <®_1v8_vdd_ddr2>;
|
|
vinldo23-supply = <®_module_3v3>;
|
|
vinldo4-supply = <®_module_3v3>;
|
|
vinldo678-supply = <®_module_3v3>;
|
|
vinldo9-supply = <®_module_3v3>;
|
|
|
|
regulators {
|
|
reg_3v3_vsys: sys {
|
|
regulator-name = "VSYS_3.3V";
|
|
regulator-always-on;
|
|
};
|
|
|
|
vdd_core: sm0 {
|
|
regulator-name = "VDD_CORE_1.2V";
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
sm1 {
|
|
regulator-name = "VDD_CPU_1.0V";
|
|
regulator-min-microvolt = <1000000>;
|
|
regulator-max-microvolt = <1000000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
reg_1v8_vdd_ddr2: sm2 {
|
|
regulator-name = "VDD_DDR2_1.8V";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
/* LDO0 is not connected to anything */
|
|
|
|
/*
|
|
* +3.3V_ENABLE_N switching via FET:
|
|
* AVDD_AUDIO_S and +3.3V
|
|
* see also +3.3V fixed supply
|
|
*/
|
|
ldo1 {
|
|
regulator-name = "AVDD_PLL_1.1V";
|
|
regulator-min-microvolt = <1100000>;
|
|
regulator-max-microvolt = <1100000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo2 {
|
|
regulator-name = "VDD_RTC_1.2V";
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
};
|
|
|
|
/* LDO3 is not connected to anything */
|
|
|
|
ldo4 {
|
|
regulator-name = "VDDIO_SYS_1.8V";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
/* Switched via FET from regular +3.3V */
|
|
ldo5 {
|
|
regulator-name = "+3.3V_USB";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo6 {
|
|
regulator-name = "AVDD_VDAC_2.85V";
|
|
regulator-min-microvolt = <2850000>;
|
|
regulator-max-microvolt = <2850000>;
|
|
};
|
|
|
|
reg_3v3_avdd_hdmi: ldo7 {
|
|
regulator-name = "AVDD_HDMI_3.3V";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
};
|
|
|
|
reg_1v8_avdd_hdmi_pll: ldo8 {
|
|
regulator-name = "AVDD_HDMI_PLL_1.8V";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
};
|
|
|
|
ldo9 {
|
|
regulator-name = "VDDIO_RX_DDR_2.85V";
|
|
regulator-min-microvolt = <2850000>;
|
|
regulator-max-microvolt = <2850000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo_rtc {
|
|
regulator-name = "VCC_BATT";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
};
|
|
};
|
|
|
|
/* LM95245 temperature sensor */
|
|
temp-sensor@4c {
|
|
compatible = "national,lm95245";
|
|
reg = <0x4c>;
|
|
};
|
|
};
|
|
|
|
pmc@7000e400 {
|
|
nvidia,suspend-mode = <1>;
|
|
nvidia,cpu-pwr-good-time = <5000>;
|
|
nvidia,cpu-pwr-off-time = <5000>;
|
|
nvidia,core-pwr-good-time = <3845 3845>;
|
|
nvidia,core-pwr-off-time = <3875>;
|
|
nvidia,sys-clock-req-active-high;
|
|
core-supply = <&vdd_core>;
|
|
|
|
/* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */
|
|
i2c-thermtrip {
|
|
nvidia,i2c-controller-id = <3>;
|
|
nvidia,bus-addr = <0x34>;
|
|
nvidia,reg-addr = <0x14>;
|
|
nvidia,reg-data = <0x8>;
|
|
};
|
|
};
|
|
|
|
memory-controller@7000f400 {
|
|
emc-table@83250 {
|
|
reg = <83250>;
|
|
compatible = "nvidia,tegra20-emc-table";
|
|
clock-frequency = <83250>;
|
|
nvidia,emc-registers = <0x00000005 0x00000011
|
|
0x00000004 0x00000002 0x00000004 0x00000004
|
|
0x00000001 0x0000000a 0x00000002 0x00000002
|
|
0x00000001 0x00000001 0x00000003 0x00000004
|
|
0x00000003 0x00000009 0x0000000c 0x0000025f
|
|
0x00000000 0x00000003 0x00000003 0x00000002
|
|
0x00000002 0x00000001 0x00000008 0x000000c8
|
|
0x00000003 0x00000005 0x00000003 0x0000000c
|
|
0x00000002 0x00000000 0x00000000 0x00000002
|
|
0x00000000 0x00000000 0x00000083 0x00520006
|
|
0x00000010 0x00000008 0x00000000 0x00000000
|
|
0x00000000 0x00000000 0x00000000 0x00000000>;
|
|
};
|
|
emc-table@133200 {
|
|
reg = <133200>;
|
|
compatible = "nvidia,tegra20-emc-table";
|
|
clock-frequency = <133200>;
|
|
nvidia,emc-registers = <0x00000008 0x00000019
|
|
0x00000006 0x00000002 0x00000004 0x00000004
|
|
0x00000001 0x0000000a 0x00000002 0x00000002
|
|
0x00000002 0x00000001 0x00000003 0x00000004
|
|
0x00000003 0x00000009 0x0000000c 0x0000039f
|
|
0x00000000 0x00000003 0x00000003 0x00000002
|
|
0x00000002 0x00000001 0x00000008 0x000000c8
|
|
0x00000003 0x00000007 0x00000003 0x0000000c
|
|
0x00000002 0x00000000 0x00000000 0x00000002
|
|
0x00000000 0x00000000 0x00000083 0x00510006
|
|
0x00000010 0x00000008 0x00000000 0x00000000
|
|
0x00000000 0x00000000 0x00000000 0x00000000>;
|
|
};
|
|
emc-table@166500 {
|
|
reg = <166500>;
|
|
compatible = "nvidia,tegra20-emc-table";
|
|
clock-frequency = <166500>;
|
|
nvidia,emc-registers = <0x0000000a 0x00000021
|
|
0x00000008 0x00000003 0x00000004 0x00000004
|
|
0x00000002 0x0000000a 0x00000003 0x00000003
|
|
0x00000002 0x00000001 0x00000003 0x00000004
|
|
0x00000003 0x00000009 0x0000000c 0x000004df
|
|
0x00000000 0x00000003 0x00000003 0x00000003
|
|
0x00000003 0x00000001 0x00000009 0x000000c8
|
|
0x00000003 0x00000009 0x00000004 0x0000000c
|
|
0x00000002 0x00000000 0x00000000 0x00000002
|
|
0x00000000 0x00000000 0x00000083 0x004f0006
|
|
0x00000010 0x00000008 0x00000000 0x00000000
|
|
0x00000000 0x00000000 0x00000000 0x00000000>;
|
|
};
|
|
emc-table@333000 {
|
|
reg = <333000>;
|
|
compatible = "nvidia,tegra20-emc-table";
|
|
clock-frequency = <333000>;
|
|
nvidia,emc-registers = <0x00000014 0x00000041
|
|
0x0000000f 0x00000005 0x00000004 0x00000005
|
|
0x00000003 0x0000000a 0x00000005 0x00000005
|
|
0x00000004 0x00000001 0x00000003 0x00000004
|
|
0x00000003 0x00000009 0x0000000c 0x000009ff
|
|
0x00000000 0x00000003 0x00000003 0x00000005
|
|
0x00000005 0x00000001 0x0000000e 0x000000c8
|
|
0x00000003 0x00000011 0x00000006 0x0000000c
|
|
0x00000002 0x00000000 0x00000000 0x00000002
|
|
0x00000000 0x00000000 0x00000083 0x00380006
|
|
0x00000010 0x00000008 0x00000000 0x00000000
|
|
0x00000000 0x00000000 0x00000000 0x00000000>;
|
|
};
|
|
};
|
|
|
|
/* EHCI instance 1: ULPI PHY -> AX88772B (On-module) */
|
|
usb@c5004000 {
|
|
status = "okay";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
ethernet@1 {
|
|
compatible = "usbb95,772b";
|
|
reg = <1>;
|
|
local-mac-address = [00 00 00 00 00 00];
|
|
};
|
|
};
|
|
|
|
usb-phy@c5004000 {
|
|
status = "okay";
|
|
nvidia,phy-reset-gpio =
|
|
<&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
|
|
vbus-supply = <®_lan_v_bus>;
|
|
};
|
|
|
|
clk32k_in: xtal3 {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
|
|
reg_lan_v_bus: regulator-lan-v-bus {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "LAN_V_BUS";
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5000000>;
|
|
enable-active-high;
|
|
gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
reg_module_3v3: regulator-module-3v3 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "+V3.3";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
sound {
|
|
compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
|
|
"nvidia,tegra-audio-wm9712";
|
|
nvidia,model = "Toradex Colibri T20";
|
|
nvidia,audio-routing =
|
|
"Headphone", "HPOUTL",
|
|
"Headphone", "HPOUTR",
|
|
"LineIn", "LINEINL",
|
|
"LineIn", "LINEINR",
|
|
"Mic", "MIC1";
|
|
nvidia,ac97-controller = <&tegra_ac97>;
|
|
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
|
|
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
|
|
<&tegra_car TEGRA20_CLK_CDEV1>;
|
|
clock-names = "pll_a", "pll_a_out0", "mclk";
|
|
};
|
|
};
|
|
|
|
&emc_icc_dvfs_opp_table {
|
|
/delete-node/ opp-760000000;
|
|
};
|
|
|
|
&gpio {
|
|
lan-reset-n-hog {
|
|
gpio-hog;
|
|
gpios = <TEGRA_GPIO(V, 4) GPIO_ACTIVE_HIGH>;
|
|
output-high;
|
|
line-name = "LAN_RESET#";
|
|
};
|
|
|
|
/* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */
|
|
npwe-hog {
|
|
gpio-hog;
|
|
gpios = <TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
|
|
output-high;
|
|
line-name = "Tri-state nPWE";
|
|
};
|
|
|
|
/* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */
|
|
rdnwr-hog {
|
|
gpio-hog;
|
|
gpios = <TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>;
|
|
output-low;
|
|
line-name = "Not tri-state RDnWR";
|
|
};
|
|
};
|