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2dbe13dbc1
DMA was never supported by i2c-omap driver and the bindings were never documented. Therefore drop the entries in preparation to moving bindings to YAML schema. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
692 lines
16 KiB
Text
692 lines
16 KiB
Text
/*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/bus/ti-sysc.h>
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#include <dt-bindings/clock/dm816.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/omap.h>
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/ {
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compatible = "ti,dm816";
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interrupt-parent = <&intc>;
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#address-cells = <1>;
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#size-cells = <1>;
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chosen { };
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aliases {
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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ethernet0 = ð0;
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ethernet1 = ð1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a8";
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device_type = "cpu";
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reg = <0>;
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};
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};
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pmu {
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compatible = "arm,cortex-a8-pmu";
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interrupts = <3>;
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};
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/*
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* The soc node represents the soc top level view. It is used for IPs
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* that are not memory mapped in the MPU view or for the MPU itself.
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*/
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soc {
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compatible = "ti,omap-infra";
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mpu {
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compatible = "ti,omap3-mpu";
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ti,hwmods = "mpu";
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};
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};
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/*
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* XXX: Use a flat representation of the dm816x interconnect.
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* The real dm816x interconnect network is quite complex. Since
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* it will not bring real advantage to represent that in DT
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* for the moment, just use a fake OCP bus entry to represent
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* the whole bus hierarchy.
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*/
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ocp {
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compatible = "simple-bus";
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reg = <0x44000000 0x10000>;
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interrupts = <9 10>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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prcm: prcm@48180000 {
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compatible = "ti,dm816-prcm", "simple-bus";
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reg = <0x48180000 0x4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x48180000 0x4000>;
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prcm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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prcm_clockdomains: clockdomains {
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};
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};
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scrm: scrm@48140000 {
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compatible = "ti,dm816-scrm", "simple-bus";
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reg = <0x48140000 0x21000>;
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#address-cells = <1>;
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#size-cells = <1>;
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#pinctrl-cells = <1>;
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ranges = <0 0x48140000 0x21000>;
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dm816x_pinmux: pinmux@800 {
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compatible = "pinctrl-single";
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reg = <0x800 0x50a>;
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#address-cells = <1>;
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#size-cells = <0>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0xf>;
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};
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/* Device Configuration Registers */
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scm_conf: syscon@600 {
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compatible = "syscon", "simple-bus";
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reg = <0x600 0x110>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x600 0x110>;
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usb_phy0: usb-phy@20 {
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compatible = "ti,dm8168-usb-phy";
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reg = <0x20 0x8>;
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reg-names = "phy";
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clocks = <&main_fapll 6>;
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clock-names = "refclk";
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#phy-cells = <0>;
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syscon = <&scm_conf>;
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};
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usb_phy1: usb-phy@28 {
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compatible = "ti,dm8168-usb-phy";
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reg = <0x28 0x8>;
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reg-names = "phy";
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clocks = <&main_fapll 6>;
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clock-names = "refclk";
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#phy-cells = <0>;
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syscon = <&scm_conf>;
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};
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};
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scrm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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scrm_clockdomains: clockdomains {
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};
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};
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target-module@49000000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49000000 0x4>;
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reg-names = "rev";
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clocks = <&alwon_clkctrl DM816_TPCC_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49000000 0x10000>;
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edma: dma@0 {
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compatible = "ti,edma3-tpcc";
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reg = <0 0x10000>;
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reg-names = "edma3_cc";
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interrupts = <12 13 14>;
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interrupt-names = "edma3_ccint", "edma3_mperr",
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"edma3_ccerrint";
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dma-requests = <64>;
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#dma-cells = <2>;
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ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
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<&edma_tptc2 3>, <&edma_tptc3 0>;
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ti,edma-memcpy-channels = <20 21>;
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};
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};
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target-module@49800000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49800000 0x4>,
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<0x49800010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_SMART>;
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clocks = <&alwon_clkctrl DM816_TPTC0_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49800000 0x100000>;
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edma_tptc0: dma@0 {
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compatible = "ti,edma3-tptc";
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reg = <0 0x100000>;
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interrupts = <112>;
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interrupt-names = "edma3_tcerrint";
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};
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};
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target-module@49900000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49900000 0x4>,
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<0x49900010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_SMART>;
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clocks = <&alwon_clkctrl DM816_TPTC1_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49900000 0x100000>;
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edma_tptc1: dma@0 {
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compatible = "ti,edma3-tptc";
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reg = <0 0x100000>;
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interrupts = <113>;
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interrupt-names = "edma3_tcerrint";
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};
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};
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target-module@49a00000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49a00000 0x4>,
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<0x49a00010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_SMART>;
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clocks = <&alwon_clkctrl DM816_TPTC2_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49a00000 0x100000>;
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edma_tptc2: dma@0 {
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compatible = "ti,edma3-tptc";
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reg = <0 0x100000>;
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interrupts = <114>;
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interrupt-names = "edma3_tcerrint";
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};
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};
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target-module@49b00000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49b00000 0x4>,
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<0x49b00010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_SMART>;
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clocks = <&alwon_clkctrl DM816_TPTC3_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49b00000 0x100000>;
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edma_tptc3: dma@0 {
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compatible = "ti,edma3-tptc";
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reg = <0 0x100000>;
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interrupts = <115>;
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interrupt-names = "edma3_tcerrint";
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};
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};
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elm: elm@48080000 {
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compatible = "ti,am3352-elm";
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ti,hwmods = "elm";
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reg = <0x48080000 0x2000>;
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interrupts = <4>;
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};
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gpio1: gpio@48032000 {
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compatible = "ti,omap4-gpio";
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ti,hwmods = "gpio1";
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ti,gpio-always-on;
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reg = <0x48032000 0x1000>;
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interrupts = <96>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@4804c000 {
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compatible = "ti,omap4-gpio";
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ti,hwmods = "gpio2";
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ti,gpio-always-on;
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reg = <0x4804c000 0x1000>;
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interrupts = <98>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpmc: gpmc@50000000 {
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compatible = "ti,am3352-gpmc";
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ti,hwmods = "gpmc";
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reg = <0x50000000 0x2000>;
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#address-cells = <2>;
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#size-cells = <1>;
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interrupts = <100>;
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dmas = <&edma 52 0>;
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dma-names = "rxtx";
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gpmc,num-cs = <6>;
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gpmc,num-waitpins = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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i2c1: i2c@48028000 {
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compatible = "ti,omap4-i2c";
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ti,hwmods = "i2c1";
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reg = <0x48028000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <70>;
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};
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i2c2: i2c@4802a000 {
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compatible = "ti,omap4-i2c";
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ti,hwmods = "i2c2";
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reg = <0x4802a000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <71>;
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};
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intc: interrupt-controller@48200000 {
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compatible = "ti,dm816-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x48200000 0x1000>;
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};
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rtc: rtc@480c0000 {
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compatible = "ti,am3352-rtc", "ti,da830-rtc";
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reg = <0x480c0000 0x1000>;
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interrupts = <75 76>;
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ti,hwmods = "rtc";
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};
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mailbox: mailbox@480c8000 {
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compatible = "ti,omap4-mailbox";
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reg = <0x480c8000 0x2000>;
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interrupts = <77>;
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ti,hwmods = "mailbox";
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <12>;
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mbox_dsp: mbox-dsp {
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ti,mbox-tx = <3 0 0>;
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ti,mbox-rx = <0 0 0>;
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};
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};
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spinbox: spinbox@480ca000 {
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compatible = "ti,omap4-hwspinlock";
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reg = <0x480ca000 0x2000>;
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ti,hwmods = "spinbox";
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#hwlock-cells = <1>;
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};
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mdio: mdio@4a100800 {
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compatible = "ti,davinci_mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x4a100800 0x100>;
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ti,hwmods = "davinci_mdio";
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bus_freq = <1000000>;
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phy0: ethernet-phy@0 {
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reg = <1>;
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};
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phy1: ethernet-phy@1 {
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reg = <2>;
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};
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};
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eth0: ethernet@4a100000 {
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compatible = "ti,dm816-emac";
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ti,hwmods = "emac0";
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reg = <0x4a100000 0x800
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0x4a100900 0x3700>;
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clocks = <&sysclk24_ck>;
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syscon = <&scm_conf>;
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ti,davinci-ctrl-reg-offset = <0>;
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ti,davinci-ctrl-mod-reg-offset = <0x900>;
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ti,davinci-ctrl-ram-offset = <0x2000>;
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ti,davinci-ctrl-ram-size = <0x2000>;
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interrupts = <40 41 42 43>;
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phy-handle = <&phy0>;
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};
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eth1: ethernet@4a120000 {
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compatible = "ti,dm816-emac";
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ti,hwmods = "emac1";
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reg = <0x4a120000 0x4000>;
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clocks = <&sysclk24_ck>;
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syscon = <&scm_conf>;
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ti,davinci-ctrl-reg-offset = <0>;
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ti,davinci-ctrl-mod-reg-offset = <0x900>;
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ti,davinci-ctrl-ram-offset = <0x2000>;
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ti,davinci-ctrl-ram-size = <0x2000>;
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interrupts = <44 45 46 47>;
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phy-handle = <&phy1>;
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};
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sata: sata@4a140000 {
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compatible = "ti,dm816-ahci";
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reg = <0x4a140000 0x10000>;
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interrupts = <16>;
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ti,hwmods = "sata";
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};
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mcspi1: spi@48030000 {
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compatible = "ti,omap4-mcspi";
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reg = <0x48030000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <65>;
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ti,spi-num-cs = <4>;
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ti,hwmods = "mcspi1";
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dmas = <&edma 16 0 &edma 17 0
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&edma 18 0 &edma 19 0
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&edma 20 0 &edma 21 0
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&edma 22 0 &edma 23 0>;
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dma-names = "tx0", "rx0", "tx1", "rx1",
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"tx2", "rx2", "tx3", "rx3";
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};
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mmc1: mmc@48060000 {
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compatible = "ti,omap4-hsmmc";
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reg = <0x48060000 0x11000>;
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ti,hwmods = "mmc1";
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interrupts = <64>;
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dmas = <&edma 24 0 &edma 25 0>;
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dma-names = "tx", "rx";
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};
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timer1_target: target-module@4802e000 {
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compatible = "ti,sysc-omap4-timer", "ti,sysc";
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reg = <0x4802e000 0x4>,
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<0x4802e010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x4802e000 0x1000>;
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timer1: timer@0 {
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compatible = "ti,dm816-timer";
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reg = <0 0x1000>;
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interrupts = <67>;
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ti,timer-alwon;
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clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
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clock-names = "fck";
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};
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};
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timer2_target: target-module@48040000 {
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compatible = "ti,sysc-omap4-timer", "ti,sysc";
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reg = <0x48040000 0x4>,
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<0x48040010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x48040000 0x1000>;
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timer2: timer@0 {
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compatible = "ti,dm816-timer";
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reg = <0 0x1000>;
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interrupts = <68>;
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clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
};
|
|
};
|
|
|
|
timer3: timer@48042000 {
|
|
compatible = "ti,dm816-timer";
|
|
reg = <0x48042000 0x2000>;
|
|
interrupts = <69>;
|
|
ti,hwmods = "timer3";
|
|
};
|
|
|
|
timer4: timer@48044000 {
|
|
compatible = "ti,dm816-timer";
|
|
reg = <0x48044000 0x2000>;
|
|
interrupts = <92>;
|
|
ti,hwmods = "timer4";
|
|
ti,timer-pwm;
|
|
};
|
|
|
|
timer5: timer@48046000 {
|
|
compatible = "ti,dm816-timer";
|
|
reg = <0x48046000 0x2000>;
|
|
interrupts = <93>;
|
|
ti,hwmods = "timer5";
|
|
ti,timer-pwm;
|
|
};
|
|
|
|
timer6: timer@48048000 {
|
|
compatible = "ti,dm816-timer";
|
|
reg = <0x48048000 0x2000>;
|
|
interrupts = <94>;
|
|
ti,hwmods = "timer6";
|
|
ti,timer-pwm;
|
|
};
|
|
|
|
timer7: timer@4804a000 {
|
|
compatible = "ti,dm816-timer";
|
|
reg = <0x4804a000 0x2000>;
|
|
interrupts = <95>;
|
|
ti,hwmods = "timer7";
|
|
ti,timer-pwm;
|
|
};
|
|
|
|
uart1: uart@48020000 {
|
|
compatible = "ti,am3352-uart", "ti,omap3-uart";
|
|
ti,hwmods = "uart1";
|
|
reg = <0x48020000 0x2000>;
|
|
clock-frequency = <48000000>;
|
|
interrupts = <72>;
|
|
dmas = <&edma 26 0 &edma 27 0>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
uart2: uart@48022000 {
|
|
compatible = "ti,am3352-uart", "ti,omap3-uart";
|
|
ti,hwmods = "uart2";
|
|
reg = <0x48022000 0x2000>;
|
|
clock-frequency = <48000000>;
|
|
interrupts = <73>;
|
|
dmas = <&edma 28 0 &edma 29 0>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
uart3: uart@48024000 {
|
|
compatible = "ti,am3352-uart", "ti,omap3-uart";
|
|
ti,hwmods = "uart3";
|
|
reg = <0x48024000 0x2000>;
|
|
clock-frequency = <48000000>;
|
|
interrupts = <74>;
|
|
dmas = <&edma 30 0 &edma 31 0>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
/* NOTE: USB needs a transceiver driver for phys to work */
|
|
usb: usb_otg_hs@47401000 {
|
|
compatible = "ti,am33xx-usb";
|
|
reg = <0x47401000 0x400000>;
|
|
ranges;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ti,hwmods = "usb_otg_hs";
|
|
|
|
usb0: usb@47401000 {
|
|
compatible = "ti,musb-dm816";
|
|
reg = <0x47401400 0x400
|
|
0x47401000 0x200>;
|
|
reg-names = "mc", "control";
|
|
interrupts = <18>;
|
|
interrupt-names = "mc";
|
|
dr_mode = "host";
|
|
interface-type = <0>;
|
|
phys = <&usb_phy0>;
|
|
phy-names = "usb2-phy";
|
|
mentor,multipoint = <1>;
|
|
mentor,num-eps = <16>;
|
|
mentor,ram-bits = <12>;
|
|
mentor,power = <500>;
|
|
|
|
dmas = <&cppi41dma 0 0 &cppi41dma 1 0
|
|
&cppi41dma 2 0 &cppi41dma 3 0
|
|
&cppi41dma 4 0 &cppi41dma 5 0
|
|
&cppi41dma 6 0 &cppi41dma 7 0
|
|
&cppi41dma 8 0 &cppi41dma 9 0
|
|
&cppi41dma 10 0 &cppi41dma 11 0
|
|
&cppi41dma 12 0 &cppi41dma 13 0
|
|
&cppi41dma 14 0 &cppi41dma 0 1
|
|
&cppi41dma 1 1 &cppi41dma 2 1
|
|
&cppi41dma 3 1 &cppi41dma 4 1
|
|
&cppi41dma 5 1 &cppi41dma 6 1
|
|
&cppi41dma 7 1 &cppi41dma 8 1
|
|
&cppi41dma 9 1 &cppi41dma 10 1
|
|
&cppi41dma 11 1 &cppi41dma 12 1
|
|
&cppi41dma 13 1 &cppi41dma 14 1>;
|
|
dma-names =
|
|
"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
|
|
"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
|
|
"rx14", "rx15",
|
|
"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
|
|
"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
|
|
"tx14", "tx15";
|
|
};
|
|
|
|
usb1: usb@47401800 {
|
|
compatible = "ti,musb-dm816";
|
|
reg = <0x47401c00 0x400
|
|
0x47401800 0x200>;
|
|
reg-names = "mc", "control";
|
|
interrupts = <19>;
|
|
interrupt-names = "mc";
|
|
dr_mode = "host";
|
|
interface-type = <0>;
|
|
phys = <&usb_phy1>;
|
|
phy-names = "usb2-phy";
|
|
mentor,multipoint = <1>;
|
|
mentor,num-eps = <16>;
|
|
mentor,ram-bits = <12>;
|
|
mentor,power = <500>;
|
|
|
|
dmas = <&cppi41dma 15 0 &cppi41dma 16 0
|
|
&cppi41dma 17 0 &cppi41dma 18 0
|
|
&cppi41dma 19 0 &cppi41dma 20 0
|
|
&cppi41dma 21 0 &cppi41dma 22 0
|
|
&cppi41dma 23 0 &cppi41dma 24 0
|
|
&cppi41dma 25 0 &cppi41dma 26 0
|
|
&cppi41dma 27 0 &cppi41dma 28 0
|
|
&cppi41dma 29 0 &cppi41dma 15 1
|
|
&cppi41dma 16 1 &cppi41dma 17 1
|
|
&cppi41dma 18 1 &cppi41dma 19 1
|
|
&cppi41dma 20 1 &cppi41dma 21 1
|
|
&cppi41dma 22 1 &cppi41dma 23 1
|
|
&cppi41dma 24 1 &cppi41dma 25 1
|
|
&cppi41dma 26 1 &cppi41dma 27 1
|
|
&cppi41dma 28 1 &cppi41dma 29 1>;
|
|
dma-names =
|
|
"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
|
|
"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
|
|
"rx14", "rx15",
|
|
"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
|
|
"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
|
|
"tx14", "tx15";
|
|
};
|
|
|
|
cppi41dma: dma-controller@47402000 {
|
|
compatible = "ti,am3359-cppi41";
|
|
reg = <0x47400000 0x1000
|
|
0x47402000 0x1000
|
|
0x47403000 0x1000
|
|
0x47404000 0x4000>;
|
|
reg-names = "glue", "controller", "scheduler", "queuemgr";
|
|
interrupts = <17>;
|
|
interrupt-names = "glue";
|
|
#dma-cells = <2>;
|
|
#dma-channels = <30>;
|
|
#dma-requests = <256>;
|
|
};
|
|
};
|
|
|
|
wd_timer2: wd_timer@480c2000 {
|
|
compatible = "ti,omap3-wdt";
|
|
ti,hwmods = "wd_timer";
|
|
reg = <0x480c2000 0x1000>;
|
|
interrupts = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "dm816x-clocks.dtsi"
|
|
|
|
/* Preferred always-on timer for clocksource */
|
|
&timer1_target {
|
|
ti,no-reset-on-init;
|
|
ti,no-idle;
|
|
timer@0 {
|
|
assigned-clocks = <&timer1_fck>;
|
|
assigned-clock-parents = <&sys_clkin_ck>;
|
|
};
|
|
};
|
|
|
|
/* Preferred timer for clockevent */
|
|
&timer2_target {
|
|
ti,no-reset-on-init;
|
|
ti,no-idle;
|
|
timer@0 {
|
|
assigned-clocks = <&timer2_fck>;
|
|
assigned-clock-parents = <&sys_clkin_ck>;
|
|
};
|
|
};
|