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1c8d7b0a56
Add the new API pci_enable_msi_block() to allow drivers to request multiple MSI and reimplement pci_enable_msi in terms of pci_enable_msi_block. Ensure that the architecture back ends don't have to know about multiple MSI. Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
36 lines
1.5 KiB
C
36 lines
1.5 KiB
C
/*
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* Copyright (C) 2003-2004 Intel
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* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
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*/
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#ifndef MSI_H
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#define MSI_H
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#define PCI_MSIX_ENTRY_SIZE 16
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#define PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET 0
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#define PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET 4
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#define PCI_MSIX_ENTRY_DATA_OFFSET 8
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#define PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET 12
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#define msi_control_reg(base) (base + PCI_MSI_FLAGS)
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#define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO)
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#define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI)
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#define msi_data_reg(base, is64bit) \
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( (is64bit == 1) ? base+PCI_MSI_DATA_64 : base+PCI_MSI_DATA_32 )
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#define msi_mask_bits_reg(base, is64bit) \
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( (is64bit == 1) ? base+PCI_MSI_MASK_BIT : base+PCI_MSI_MASK_BIT-4)
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#define msi_disable(control) control &= ~PCI_MSI_FLAGS_ENABLE
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#define is_64bit_address(control) (!!(control & PCI_MSI_FLAGS_64BIT))
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#define is_mask_bit_support(control) (!!(control & PCI_MSI_FLAGS_MASKBIT))
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#define msix_table_offset_reg(base) (base + 0x04)
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#define msix_pba_offset_reg(base) (base + 0x08)
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#define msix_enable(control) control |= PCI_MSIX_FLAGS_ENABLE
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#define msix_disable(control) control &= ~PCI_MSIX_FLAGS_ENABLE
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#define msix_table_size(control) ((control & PCI_MSIX_FLAGS_QSIZE)+1)
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#define multi_msix_capable msix_table_size
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#define msix_unmask(address) (address & ~PCI_MSIX_FLAGS_BITMASK)
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#define msix_mask(address) (address | PCI_MSIX_FLAGS_BITMASK)
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#define msix_is_pending(address) (address & PCI_MSIX_FLAGS_PENDMASK)
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#endif /* MSI_H */
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