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linux/drivers/gpu/drm/msm/dsi
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Archit Taneja c1d97083cd drm/msm/dsi: Add byte_intf_clk 
DSI6G v2.0+ blocks have a new clock input to them called
byte_intf_clk. It's rate is to be set as byte_clk / 2.

Within the clock controller (CC) subsystem, this clock is a
child/descendant of the byte_clk.

Set it up as an optional clock in the DSI host driver. Make sure
that we enable/set its rate only after we configure byte_clk.
This is required for the ancestor clocks in the CC to be
configured correctly.

Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-02-20 10:41:21 -05:00
..
phy drm/msm/dsi: Populate the 10nm PHY funcs 2018-02-20 10:41:21 -05:00
pll drm/msm/dsi: Populate PLL 10nm clock ops 2018-02-20 10:41:20 -05:00
dsi.c drm/msm/dsi: check msm_dsi and dsi pointers before use 2018-02-20 10:41:20 -05:00
dsi.h drm/msm/dsi: Add skeleton 10nm PHY/PLL code 2018-02-20 10:41:20 -05:00
dsi.xml.h drm/msm/dsi: Update generated headers for 10nm PLL/PHY 2018-02-20 10:41:20 -05:00
dsi_cfg.c drm/msm/dsi: Add SDM845 in dsi_cfg 2018-02-20 10:41:21 -05:00
dsi_cfg.h drm/msm/dsi: Add SDM845 in dsi_cfg 2018-02-20 10:41:21 -05:00
dsi_host.c drm/msm/dsi: Add byte_intf_clk 2018-02-20 10:41:21 -05:00
dsi_manager.c drm/msm/dsi: correct DSI id bounds check during registration 2018-02-20 10:41:20 -05:00
mmss_cc.xml.h drm/msm: update generated headers 2017-06-16 11:16:07 -04:00
sfpb.xml.h drm/msm: update generated headers 2017-06-16 11:16:07 -04:00