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c0071c7aa5
Add code for hardware initialization and reset Add code for semaphore handling Signed-off-by: Sasha Neftin <sasha.neftin@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
209 lines
8 KiB
C
209 lines
8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018 Intel Corporation */
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#ifndef _IGC_DEFINES_H_
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#define _IGC_DEFINES_H_
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#define IGC_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */
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/* PCI Bus Info */
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#define PCIE_DEVICE_CONTROL2 0x28
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#define PCIE_DEVICE_CONTROL2_16ms 0x0005
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/* Physical Func Reset Done Indication */
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#define IGC_CTRL_EXT_LINK_MODE_MASK 0x00C00000
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/* Number of 100 microseconds we wait for PCI Express master disable */
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#define MASTER_DISABLE_TIMEOUT 800
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/*Blocks new Master requests */
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#define IGC_CTRL_GIO_MASTER_DISABLE 0x00000004
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/* Status of Master requests. */
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#define IGC_STATUS_GIO_MASTER_ENABLE 0x00080000
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/* PCI Express Control */
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#define IGC_GCR_CMPL_TMOUT_MASK 0x0000F000
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#define IGC_GCR_CMPL_TMOUT_10ms 0x00001000
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#define IGC_GCR_CMPL_TMOUT_RESEND 0x00010000
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#define IGC_GCR_CAP_VER2 0x00040000
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/* Receive Address
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* Number of high/low register pairs in the RAR. The RAR (Receive Address
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* Registers) holds the directed and multicast addresses that we monitor.
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* Technically, we have 16 spots. However, we reserve one of these spots
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* (RAR[15]) for our directed address used by controllers with
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* manageability enabled, allowing us room for 15 multicast addresses.
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*/
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#define IGC_RAH_AV 0x80000000 /* Receive descriptor valid */
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#define IGC_RAH_POOL_1 0x00040000
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/* Error Codes */
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#define IGC_SUCCESS 0
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#define IGC_ERR_NVM 1
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#define IGC_ERR_PHY 2
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#define IGC_ERR_CONFIG 3
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#define IGC_ERR_PARAM 4
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#define IGC_ERR_MAC_INIT 5
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#define IGC_ERR_RESET 9
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#define IGC_ERR_MASTER_REQUESTS_PENDING 10
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#define IGC_ERR_SWFW_SYNC 13
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/* Device Control */
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#define IGC_CTRL_RST 0x04000000 /* Global reset */
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/* PBA constants */
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#define IGC_PBA_34K 0x0022
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/* SW Semaphore Register */
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#define IGC_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
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#define IGC_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
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/* Number of milliseconds for NVM auto read done after MAC reset. */
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#define AUTO_READ_DONE_TIMEOUT 10
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#define IGC_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
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/* Device Status */
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#define IGC_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
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#define IGC_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
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#define IGC_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
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#define IGC_STATUS_FUNC_SHIFT 2
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#define IGC_STATUS_FUNC_1 0x00000004 /* Function 1 */
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#define IGC_STATUS_TXOFF 0x00000010 /* transmission paused */
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#define IGC_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
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#define IGC_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
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/* Interrupt Cause Read */
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#define IGC_ICR_TXDW BIT(0) /* Transmit desc written back */
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#define IGC_ICR_TXQE BIT(1) /* Transmit Queue empty */
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#define IGC_ICR_LSC BIT(2) /* Link Status Change */
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#define IGC_ICR_RXSEQ BIT(3) /* Rx sequence error */
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#define IGC_ICR_RXDMT0 BIT(4) /* Rx desc min. threshold (0) */
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#define IGC_ICR_RXO BIT(6) /* Rx overrun */
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#define IGC_ICR_RXT0 BIT(7) /* Rx timer intr (ring 0) */
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#define IGC_ICR_DRSTA BIT(30) /* Device Reset Asserted */
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/* If this bit asserted, the driver should claim the interrupt */
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#define IGC_ICR_INT_ASSERTED BIT(31)
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#define IGC_ICS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
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#define IMS_ENABLE_MASK ( \
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IGC_IMS_RXT0 | \
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IGC_IMS_TXDW | \
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IGC_IMS_RXDMT0 | \
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IGC_IMS_RXSEQ | \
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IGC_IMS_LSC)
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/* Interrupt Mask Set */
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#define IGC_IMS_TXDW IGC_ICR_TXDW /* Tx desc written back */
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#define IGC_IMS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */
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#define IGC_IMS_LSC IGC_ICR_LSC /* Link Status Change */
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#define IGC_IMS_DOUTSYNC IGC_ICR_DOUTSYNC /* NIC DMA out of sync */
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#define IGC_IMS_DRSTA IGC_ICR_DRSTA /* Device Reset Asserted */
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#define IGC_IMS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
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#define IGC_IMS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */
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#define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
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#define IGC_ITR_VAL_MASK 0x04 /* ITR value mask */
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#define IGC_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
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#define IGC_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
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#define IGC_IVAR_VALID 0x80
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#define IGC_GPIE_NSICR 0x00000001
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#define IGC_GPIE_MSIX_MODE 0x00000010
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#define IGC_GPIE_EIAME 0x40000000
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#define IGC_GPIE_PBA 0x80000000
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/* Transmit Descriptor bit definitions */
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#define IGC_TXD_DTYP_D 0x00100000 /* Data Descriptor */
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#define IGC_TXD_DTYP_C 0x00000000 /* Context Descriptor */
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#define IGC_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
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#define IGC_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
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#define IGC_TXD_CMD_EOP 0x01000000 /* End of Packet */
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#define IGC_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
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#define IGC_TXD_CMD_IC 0x04000000 /* Insert Checksum */
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#define IGC_TXD_CMD_RS 0x08000000 /* Report Status */
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#define IGC_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
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#define IGC_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */
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#define IGC_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
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#define IGC_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
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#define IGC_TXD_STAT_DD 0x00000001 /* Descriptor Done */
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#define IGC_TXD_STAT_EC 0x00000002 /* Excess Collisions */
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#define IGC_TXD_STAT_LC 0x00000004 /* Late Collisions */
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#define IGC_TXD_STAT_TU 0x00000008 /* Transmit underrun */
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#define IGC_TXD_CMD_TCP 0x01000000 /* TCP packet */
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#define IGC_TXD_CMD_IP 0x02000000 /* IP packet */
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#define IGC_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
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#define IGC_TXD_STAT_TC 0x00000004 /* Tx Underrun */
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#define IGC_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */
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/* Transmit Control */
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#define IGC_TCTL_EN 0x00000002 /* enable Tx */
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#define IGC_TCTL_PSP 0x00000008 /* pad short packets */
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#define IGC_TCTL_CT 0x00000ff0 /* collision threshold */
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#define IGC_TCTL_COLD 0x003ff000 /* collision distance */
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#define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
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#define IGC_TCTL_MULR 0x10000000 /* Multiple request support */
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#define IGC_CT_SHIFT 4
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#define IGC_COLLISION_THRESHOLD 15
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/* Flow Control Constants */
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#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
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#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
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#define FLOW_CONTROL_TYPE 0x8808
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/* Enable XON frame transmission */
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#define IGC_FCRTL_XONE 0x80000000
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/* Management Control */
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#define IGC_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
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/* Receive Control */
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#define IGC_RCTL_RST 0x00000001 /* Software reset */
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#define IGC_RCTL_EN 0x00000002 /* enable */
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#define IGC_RCTL_SBP 0x00000004 /* store bad packet */
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#define IGC_RCTL_UPE 0x00000008 /* unicast promisc enable */
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#define IGC_RCTL_MPE 0x00000010 /* multicast promisc enable */
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#define IGC_RCTL_LPE 0x00000020 /* long packet enable */
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#define IGC_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
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#define IGC_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
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#define IGC_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
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#define IGC_RCTL_BAM 0x00008000 /* broadcast enable */
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/* Receive Descriptor bit definitions */
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#define IGC_RXD_STAT_EOP 0x02 /* End of Packet */
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#define IGC_RXDEXT_STATERR_CE 0x01000000
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#define IGC_RXDEXT_STATERR_SE 0x02000000
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#define IGC_RXDEXT_STATERR_SEQ 0x04000000
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#define IGC_RXDEXT_STATERR_CXE 0x10000000
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#define IGC_RXDEXT_STATERR_TCPE 0x20000000
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#define IGC_RXDEXT_STATERR_IPE 0x40000000
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#define IGC_RXDEXT_STATERR_RXE 0x80000000
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/* Same mask, but for extended and packet split descriptors */
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#define IGC_RXDEXT_ERR_FRAME_ERR_MASK ( \
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IGC_RXDEXT_STATERR_CE | \
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IGC_RXDEXT_STATERR_SE | \
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IGC_RXDEXT_STATERR_SEQ | \
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IGC_RXDEXT_STATERR_CXE | \
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IGC_RXDEXT_STATERR_RXE)
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/* Header split receive */
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#define IGC_RFCTL_IPV6_EX_DIS 0x00010000
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#define IGC_RFCTL_LEF 0x00040000
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#define IGC_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
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#define IGC_RCTL_MO_SHIFT 12 /* multicast offset shift */
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#define IGC_RCTL_CFIEN 0x00080000 /* canonical form enable */
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#define IGC_RCTL_DPF 0x00400000 /* discard pause frames */
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#define IGC_RCTL_PMCF 0x00800000 /* pass MAC control frames */
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#define IGC_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
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#define I225_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */
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#define I225_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */
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#define IGC_N0_QUEUE -1
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#endif /* _IGC_DEFINES_H_ */
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