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bf926731e1
'closid' (CLass Of Service ID) is used for the Class based Cache Allocation Technology (CAT). Add explicit storage to the per cpu cache for it, so it can be used later with the CAT support (requires to move the per cpu data). While at it: - Rename the structure to intel_pqr_state which reflects the actual purpose of the struct: cache values which go into the PQR MSR - Rename 'cnt' to rmid_usecnt which reflects the actual purpose of the counter. - Document the structure and the struct members. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Matt Fleming <matt.fleming@intel.com> Cc: Kanaka Juvva <kanaka.d.juvva@intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Vikas Shivappa <vikas.shivappa@linux.intel.com> Cc: Will Auld <will.auld@intel.com> Link: http://lkml.kernel.org/r/20150518235150.240899319@linutronix.de Signed-off-by: Ingo Molnar <mingo@kernel.org> |
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| common.c | ||
| cpu.h | ||
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| intel.c | ||
| intel_cacheinfo.c | ||
| intel_pt.h | ||
| Makefile | ||
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| mkcapflags.sh | ||
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| perf_event.c | ||
| perf_event.h | ||
| perf_event_amd.c | ||
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| perf_event_amd_iommu.c | ||
| perf_event_amd_iommu.h | ||
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| perf_event_intel.c | ||
| perf_event_intel_bts.c | ||
| perf_event_intel_cqm.c | ||
| perf_event_intel_ds.c | ||
| perf_event_intel_lbr.c | ||
| perf_event_intel_pt.c | ||
| perf_event_intel_rapl.c | ||
| perf_event_intel_uncore.c | ||
| perf_event_intel_uncore.h | ||
| perf_event_intel_uncore_nhmex.c | ||
| perf_event_intel_uncore_snb.c | ||
| perf_event_intel_uncore_snbep.c | ||
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| powerflags.c | ||
| proc.c | ||
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| topology.c | ||
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