The flexcan IP core has up to 64 mailboxes, each one has a corresponding
interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
imask1 or imask2 registers.
The driver will always use the last mailbox for TX, which falls into the iflag2
register.
To support CANFD the payload size has to increase to 64 bytes and the number of
mailboxes will decrease so much that the TX mailbox will be handled in the
iflag1 register.
This patch add support to handle the TX mailbox independent whether it's
in iflag1 or iflag2 by introducing th flexcan_read_reg_iflag_tx()
function, similar to flexcan_read_reg_iflag_rx(), for the read path.
For the write path the function flexcan_write64() is added.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
b87c28b726