Sasha Neftin b49feacbef e1000e: Enable GPT clock before sending message to CSME ... On corporate (CSME) ADL systems, the Ethernet Controller may stop working ("HW unit hang") after exiting from the s0ix state. The reason is that CSME misses the message sent by the host. Enabling the dynamic GPT clock solves this problem. This clock is cleared upon HW initialization. Fixes: 3e55d23171 ("e1000e: Add handshake with the CSME to support S0ix") Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=214821 Reviewed-by: Dima Ruinskiy <dima.ruinskiy@intel.com> Signed-off-by: Sasha Neftin <sasha.neftin@intel.com> Tested-by: Chia-Lin Kao (AceLan) <acelan.kao@canonical.com> Tested-by: Naama Meir <naamax.meir@linux.intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>		2022-07-14 09:16:47 -07:00
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80003es2lan.c
80003es2lan.h
82571.c
82571.h
defines.h
e1000.h	e1000e: Separate ADP board type from TGP	2022-02-01 08:59:45 -08:00
ethtool.c	ethtool: extend ringparam setting/getting API with rx_buf_len	2021-11-22 12:31:49 +00:00
hw.h	e1000e: Fix possible HW unit hang after an s0ix exit	2022-02-28 13:42:28 -08:00
ich8lan.c	e1000e: Fix possible overflow in LTR decoding	2022-04-13 09:18:27 -07:00
ich8lan.h	e1000e: Fix possible HW unit hang after an s0ix exit	2022-02-28 13:42:28 -08:00
mac.c
mac.h
Makefile
manage.c
manage.h
netdev.c	e1000e: Enable GPT clock before sending message to CSME	2022-07-14 09:16:47 -07:00
nvm.c
nvm.h
param.c
phy.c	e1000e: Print PHY register address when MDI read/write fails	2022-03-09 19:53:03 -08:00
phy.h
ptp.c	e1000e: Add support for Lunar Lake	2021-07-20 16:11:36 -07:00
regs.h