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![]() Instantiate the L2 cache from DT. Indicate in DT where the cache control register is so that it is possible to enable/disable write through on the CPU. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net> |
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.. | ||
arm_timer.h | ||
cache-feroceon-l2.h | ||
cache-l2x0.h | ||
cache-tauros2.h | ||
coresight.h | ||
dec21285.h | ||
entry-macro-iomd.S | ||
icst.h | ||
ioc.h | ||
iomd.h | ||
iop3xx-adma.h | ||
iop3xx.h | ||
iop_adma.h | ||
it8152.h | ||
locomo.h | ||
memc.h | ||
sa1111.h | ||
scoop.h | ||
ssp.h | ||
timer-sp.h |