Charlene Liu bb21290ff6 drm/amd/display: Create DWB resource for DCN2 ... [Description] dcn20 has num_dwb =1 in the res cap, but not created. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Duke Du <Duke.Du@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-06-22 09:34:11 -05:00
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athub	drm/amdgpu: add ATHUB 2.0 register headers	2019-06-20 15:54:18 -05:00
bif
clk	drm/amdgpu: add CLK 11.0 register headers	2019-06-20 15:54:21 -05:00
dce
dcn	drm/amd/display: Create DWB resource for DCN2	2019-06-22 09:34:11 -05:00
df	drm/amdgpu: add df perfmon regs and funcs for xgmi	2019-05-24 12:20:50 -05:00
gc	drm/amdgpu: add GC 10.1 register headers (v4)	2019-06-20 15:54:35 -05:00
gca
gmc
hdp	drm/amdgpu: add HDP 5.0 register headers	2019-06-20 15:54:26 -05:00
mmhub	drm/amdgpu: add MMHUB 2.0 register headers	2019-06-20 15:54:39 -05:00
mp	drm/amdgpu: add MP 11.0 register headers	2019-06-20 15:54:28 -05:00
nbif
nbio	drm/amdgpu: add NBIO 2.3 register headers	2019-06-20 15:54:31 -05:00
oss	drm/amdgpu: add OSS 5.0 register headers	2019-06-20 15:54:42 -05:00
sdma0	drm/amdgpu/include: Add sdma0/1 4.2 register headerfiles. (v3)	2018-08-27 11:10:21 -05:00
sdma1	drm/amdgpu/include: Add sdma0/1 4.2 register headerfiles. (v3)	2018-08-27 11:10:21 -05:00
smu
smuio	drm/amdgpu: add SMUIO 11.0 register headers	2019-06-20 15:54:44 -05:00
thm	drm/amdgpu: update THM IP register header to support BACO	2019-01-25 16:15:33 -05:00
umc
uvd
vce
vcn	drm/amdgpu: add VCN 2.0 register headers	2019-06-20 15:54:33 -05:00