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ba36d53db5
The Aspeed SoC has timer IP with a very similar register layout to the moxart timer. This patch adds support for the fourth and fifth gen aspeed SoCs, and has been tested on the ast2400 and ast2500. Signed-off-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
19 lines
451 B
Text
19 lines
451 B
Text
MOXA ART timer
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Required properties:
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- compatible : Must be one of:
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- "moxa,moxart-timer"
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- "aspeed,ast2400-timer"
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- reg : Should contain registers location and length
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- interrupts : Should contain the timer interrupt number
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- clocks : Should contain phandle for the clock that drives the counter
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Example:
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timer: timer@98400000 {
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compatible = "moxa,moxart-timer";
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reg = <0x98400000 0x42>;
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interrupts = <19 1>;
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clocks = <&coreclk>;
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};
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