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ac4c244d4e
ARC700 has an in-core intc which provides 2 priorities (a.k.a.) "levels"
of interrupts (per IRQ) hencforth referred to as L1/L2 interrupts.
CPU flags register STATUS32 has Interrupt Enable bits per level (E1/E2)
to globally enable (or disable) all IRQs at a level. Hence the
implementation of arch_local_irq_{save,restore,enable,disable}( )
The STATUS32 reg can be r/w only using the AUX Interface of ARC, hence
the use of LR/SR instructions. Further, E1/E2 bits in there can only be
updated using the FLAG insn.
The intc supports 32 interrupts - and per IRQ enabling is controlled by
a bit in the AUX_IENABLE register, hence the implmentation of
arch_{,un}mask_irq( ) routines.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
32 lines
759 B
C
32 lines
759 B
C
/*
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* Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <asm/irqflags.h>
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#include <asm/arcregs.h>
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void arch_local_irq_enable(void)
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{
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unsigned long flags;
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/*
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* ARC IDE Drivers tries to re-enable interrupts from hard-isr
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* context which is simply wrong
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*/
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if (in_irq()) {
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WARN_ONCE(1, "IRQ enabled from hard-isr");
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return;
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}
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flags = arch_local_save_flags();
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flags |= (STATUS_E1_MASK | STATUS_E2_MASK);
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arch_local_irq_restore(flags);
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}
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EXPORT_SYMBOL(arch_local_irq_enable);
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