mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-08-05 16:54:27 +00:00
ab7c01fdc3
There are five MIPS32/64 architecture releases currently available:
from 1 to 6 except fourth one, which was intentionally skipped.
Three of them can be called as major: 1st, 2nd and 6th, that not only
have some system level alterations, but also introduced significant
core/ISA level updates. The rest of the MIPS architecture releases are
minor.
Even though they don't have as much ISA/system/core level changes
as the major ones with respect to the previous releases, they still
provide a set of updates (I'd say they were intended to be the
intermediate releases before a major one) that might be useful for the
kernel and user-level code, when activated by the kernel or compiler.
In particular the following features were introduced or ended up being
available at/after MIPS32/64 Release 5 architecture:
+ the last release of the misaligned memory access instructions,
+ virtualisation - VZ ASE - is optional component of the arch,
+ SIMD - MSA ASE - is optional component of the arch,
+ DSP ASE is optional component of the arch,
+ CP0.Status.FR=1 for CP1.FIR.F64=1 (pure 64-bit FPU general registers)
must be available if FPU is implemented,
+ CP1.FIR.Has2008 support is required so CP1.FCSR.{ABS2008,NAN2008} bits
are available.
+ UFR/UNFR aliases to access CP0.Status.FR from user-space by means of
ctc1/cfc1 instructions (enabled by CP0.Config5.UFR),
+ CP0.COnfig5.LLB=1 and eretnc instruction are implemented to without
accidentally clearing LL-bit when returning from an interrupt,
exception, or error trap,
+ XPA feature together with extended versions of CPx registers is
introduced, which needs to have mfhc0/mthc0 instructions available.
So due to these changes GNU GCC provides an extended instructions set
support for MIPS32/64 Release 5 by default like eretnc/mfhc0/mthc0. Even
though the architecture alteration isn't that big, it still worth to be
taken into account by the kernel software. Finally we can't deny that
some optimization/limitations might be found in future and implemented
on some level in kernel or compiler. In this case having even
intermediate MIPS architecture releases support would be more than
useful.
So the most of the changes provided by this commit can be split into
either compile- or runtime configs related. The compile-time related
changes are caused by adding the new CONFIG_CPU_MIPS32_R5/CONFIG_CPU_MIPSR5
configs and concern the code activating MIPSR2 or MIPSR6 already
implemented features (like eretnc/LLbit, mthc0/mfhc0). In addition
CPU_HAS_MSA can be now freely enabled for MIPS32/64 release 5 based
platforms as this is done for CPU_MIPS32_R6 CPUs. The runtime changes
concerns the features which are handled with respect to the MIPS ISA
revision detected at run-time by means of CP0.Config.{AT,AR} bits. Alas
these fields can be used to detect either r1 or r2 or r6 releases.
But since we know which CPUs in fact support the R5 arch, we can manually
set MIPS_CPU_ISA_M32R5/MIPS_CPU_ISA_M64R5 bit of c->isa_level and then
use cpu_has_mips32r5/cpu_has_mips64r5 where it's appropriate.
Since XPA/EVA provide too complex alterationss and to have them used with
MIPS32 Release 2 charged kernels (for compatibility with current platform
configs) they are left to be setup as a separate kernel configs.
Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
151 lines
4.4 KiB
C
151 lines
4.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
#ifndef _ASM_MODULE_H
|
|
#define _ASM_MODULE_H
|
|
|
|
#include <linux/list.h>
|
|
#include <linux/elf.h>
|
|
#include <asm/extable.h>
|
|
|
|
struct mod_arch_specific {
|
|
/* Data Bus Error exception tables */
|
|
struct list_head dbe_list;
|
|
const struct exception_table_entry *dbe_start;
|
|
const struct exception_table_entry *dbe_end;
|
|
struct mips_hi16 *r_mips_hi16_list;
|
|
};
|
|
|
|
typedef uint8_t Elf64_Byte; /* Type for a 8-bit quantity. */
|
|
|
|
typedef struct {
|
|
Elf64_Addr r_offset; /* Address of relocation. */
|
|
Elf64_Word r_sym; /* Symbol index. */
|
|
Elf64_Byte r_ssym; /* Special symbol. */
|
|
Elf64_Byte r_type3; /* Third relocation. */
|
|
Elf64_Byte r_type2; /* Second relocation. */
|
|
Elf64_Byte r_type; /* First relocation. */
|
|
} Elf64_Mips_Rel;
|
|
|
|
typedef struct {
|
|
Elf64_Addr r_offset; /* Address of relocation. */
|
|
Elf64_Word r_sym; /* Symbol index. */
|
|
Elf64_Byte r_ssym; /* Special symbol. */
|
|
Elf64_Byte r_type3; /* Third relocation. */
|
|
Elf64_Byte r_type2; /* Second relocation. */
|
|
Elf64_Byte r_type; /* First relocation. */
|
|
Elf64_Sxword r_addend; /* Addend. */
|
|
} Elf64_Mips_Rela;
|
|
|
|
#ifdef CONFIG_32BIT
|
|
#define Elf_Shdr Elf32_Shdr
|
|
#define Elf_Sym Elf32_Sym
|
|
#define Elf_Ehdr Elf32_Ehdr
|
|
#define Elf_Addr Elf32_Addr
|
|
#define Elf_Rel Elf32_Rel
|
|
#define Elf_Rela Elf32_Rela
|
|
#define ELF_R_TYPE(X) ELF32_R_TYPE(X)
|
|
#define ELF_R_SYM(X) ELF32_R_SYM(X)
|
|
|
|
#define Elf_Mips_Rel Elf32_Rel
|
|
#define Elf_Mips_Rela Elf32_Rela
|
|
|
|
#define ELF_MIPS_R_SYM(rel) ELF32_R_SYM((rel).r_info)
|
|
#define ELF_MIPS_R_TYPE(rel) ELF32_R_TYPE((rel).r_info)
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_64BIT
|
|
#define Elf_Shdr Elf64_Shdr
|
|
#define Elf_Sym Elf64_Sym
|
|
#define Elf_Ehdr Elf64_Ehdr
|
|
#define Elf_Addr Elf64_Addr
|
|
#define Elf_Rel Elf64_Rel
|
|
#define Elf_Rela Elf64_Rela
|
|
#define ELF_R_TYPE(X) ELF64_R_TYPE(X)
|
|
#define ELF_R_SYM(X) ELF64_R_SYM(X)
|
|
|
|
#define Elf_Mips_Rel Elf64_Mips_Rel
|
|
#define Elf_Mips_Rela Elf64_Mips_Rela
|
|
|
|
#define ELF_MIPS_R_SYM(rel) ((rel).r_sym)
|
|
#define ELF_MIPS_R_TYPE(rel) ((rel).r_type)
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_MODULES
|
|
/* Given an address, look for it in the exception tables. */
|
|
const struct exception_table_entry*search_module_dbetables(unsigned long addr);
|
|
#else
|
|
/* Given an address, look for it in the exception tables. */
|
|
static inline const struct exception_table_entry *
|
|
search_module_dbetables(unsigned long addr)
|
|
{
|
|
return NULL;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_CPU_BMIPS
|
|
#define MODULE_PROC_FAMILY "BMIPS "
|
|
#elif defined CONFIG_CPU_MIPS32_R1
|
|
#define MODULE_PROC_FAMILY "MIPS32_R1 "
|
|
#elif defined CONFIG_CPU_MIPS32_R2
|
|
#define MODULE_PROC_FAMILY "MIPS32_R2 "
|
|
#elif defined CONFIG_CPU_MIPS32_R5
|
|
#define MODULE_PROC_FAMILY "MIPS32_R5 "
|
|
#elif defined CONFIG_CPU_MIPS32_R6
|
|
#define MODULE_PROC_FAMILY "MIPS32_R6 "
|
|
#elif defined CONFIG_CPU_MIPS64_R1
|
|
#define MODULE_PROC_FAMILY "MIPS64_R1 "
|
|
#elif defined CONFIG_CPU_MIPS64_R2
|
|
#define MODULE_PROC_FAMILY "MIPS64_R2 "
|
|
#elif defined CONFIG_CPU_MIPS64_R5
|
|
#define MODULE_PROC_FAMILY "MIPS64_R5 "
|
|
#elif defined CONFIG_CPU_MIPS64_R6
|
|
#define MODULE_PROC_FAMILY "MIPS64_R6 "
|
|
#elif defined CONFIG_CPU_R3000
|
|
#define MODULE_PROC_FAMILY "R3000 "
|
|
#elif defined CONFIG_CPU_TX39XX
|
|
#define MODULE_PROC_FAMILY "TX39XX "
|
|
#elif defined CONFIG_CPU_VR41XX
|
|
#define MODULE_PROC_FAMILY "VR41XX "
|
|
#elif defined CONFIG_CPU_R4X00
|
|
#define MODULE_PROC_FAMILY "R4X00 "
|
|
#elif defined CONFIG_CPU_TX49XX
|
|
#define MODULE_PROC_FAMILY "TX49XX "
|
|
#elif defined CONFIG_CPU_R5000
|
|
#define MODULE_PROC_FAMILY "R5000 "
|
|
#elif defined CONFIG_CPU_R5500
|
|
#define MODULE_PROC_FAMILY "R5500 "
|
|
#elif defined CONFIG_CPU_NEVADA
|
|
#define MODULE_PROC_FAMILY "NEVADA "
|
|
#elif defined CONFIG_CPU_R10000
|
|
#define MODULE_PROC_FAMILY "R10000 "
|
|
#elif defined CONFIG_CPU_RM7000
|
|
#define MODULE_PROC_FAMILY "RM7000 "
|
|
#elif defined CONFIG_CPU_SB1
|
|
#define MODULE_PROC_FAMILY "SB1 "
|
|
#elif defined CONFIG_CPU_LOONGSON32
|
|
#define MODULE_PROC_FAMILY "LOONGSON32 "
|
|
#elif defined CONFIG_CPU_LOONGSON2EF
|
|
#define MODULE_PROC_FAMILY "LOONGSON2EF "
|
|
#elif defined CONFIG_CPU_LOONGSON64
|
|
#define MODULE_PROC_FAMILY "LOONGSON64 "
|
|
#elif defined CONFIG_CPU_CAVIUM_OCTEON
|
|
#define MODULE_PROC_FAMILY "OCTEON "
|
|
#elif defined CONFIG_CPU_XLR
|
|
#define MODULE_PROC_FAMILY "XLR "
|
|
#elif defined CONFIG_CPU_XLP
|
|
#define MODULE_PROC_FAMILY "XLP "
|
|
#else
|
|
#error MODULE_PROC_FAMILY undefined for your processor configuration
|
|
#endif
|
|
|
|
#ifdef CONFIG_32BIT
|
|
#define MODULE_KERNEL_TYPE "32BIT "
|
|
#elif defined CONFIG_64BIT
|
|
#define MODULE_KERNEL_TYPE "64BIT "
|
|
#endif
|
|
|
|
#define MODULE_ARCH_VERMAGIC \
|
|
MODULE_PROC_FAMILY MODULE_KERNEL_TYPE
|
|
|
|
#endif /* _ASM_MODULE_H */
|