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aa52b39dc5
This patch computes the VRR parameters from VRR crtc states and configures them in VRR registers during CRTC enable in the modeset enable sequence. v2: * Remove initialization to 0 (Jani N) * Use correct pipe %c (Jani N) v3: * Remove debug prints (Ville) * Use cpu_trans instead of pipe for TRANS_VRR regs (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-10-manasi.d.navare@intel.com
123 lines
3.9 KiB
C
123 lines
3.9 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2020 Intel Corporation
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*
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*/
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#include "i915_drv.h"
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#include "intel_display_types.h"
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#include "intel_vrr.h"
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bool intel_vrr_is_capable(struct drm_connector *connector)
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{
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struct intel_dp *intel_dp;
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const struct drm_display_info *info = &connector->display_info;
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struct drm_i915_private *i915 = to_i915(connector->dev);
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if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
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connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
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return false;
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intel_dp = intel_attached_dp(to_intel_connector(connector));
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/*
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* DP Sink is capable of VRR video timings if
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* Ignore MSA bit is set in DPCD.
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* EDID monitor range also should be atleast 10 for reasonable
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* Adaptive Sync or Variable Refresh Rate end user experience.
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*/
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return HAS_VRR(i915) &&
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drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) &&
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info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
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}
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void
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intel_vrr_check_modeset(struct intel_atomic_state *state)
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{
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int i;
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struct intel_crtc_state *old_crtc_state, *new_crtc_state;
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struct intel_crtc *crtc;
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for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
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new_crtc_state, i) {
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if (new_crtc_state->uapi.vrr_enabled !=
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old_crtc_state->uapi.vrr_enabled)
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new_crtc_state->uapi.mode_changed = true;
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}
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}
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void
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intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
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struct drm_connector_state *conn_state)
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{
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struct intel_connector *connector =
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to_intel_connector(conn_state->connector);
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struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
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const struct drm_display_info *info = &connector->base.display_info;
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int vmin, vmax;
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if (!intel_vrr_is_capable(&connector->base))
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return;
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if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
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return;
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if (!crtc_state->uapi.vrr_enabled)
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return;
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vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
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adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq);
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vmax = adjusted_mode->crtc_clock * 1000 /
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(adjusted_mode->crtc_htotal * info->monitor_range.min_vfreq);
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vmin = max_t(int, vmin, adjusted_mode->crtc_vtotal);
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vmax = max_t(int, vmax, adjusted_mode->crtc_vtotal);
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if (vmin >= vmax)
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return;
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/*
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* flipline determines the min vblank length the hardware will
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* generate, and flipline>=vmin+1, hence we reduce vmin by one
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* to make sure we can get the actual min vblank length.
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*/
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crtc_state->vrr.vmin = vmin - 1;
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crtc_state->vrr.vmax = vmax;
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crtc_state->vrr.enable = true;
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crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1;
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/*
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* FIXME: s/4/framestart_delay+1/ to get consistent
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* earliest/latest points for register latching regardless
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* of the framestart_delay used?
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*
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* FIXME: this really needs the extra scanline to provide consistent
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* behaviour for all framestart_delay values. Otherwise with
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* framestart_delay==3 we will end up extending the min vblank by
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* one extra line.
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*/
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crtc_state->vrr.pipeline_full =
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min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1);
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}
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void intel_vrr_enable(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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u32 trans_vrr_ctl;
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if (!crtc_state->vrr.enable)
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return;
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trans_vrr_ctl = VRR_CTL_VRR_ENABLE |
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VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
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VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) |
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VRR_CTL_PIPELINE_FULL_OVERRIDE;
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intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1);
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intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
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intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl);
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intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1);
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intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN);
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}
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