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a6da0d77e9
The perf_event_create_kernel_counter() in the pmc_reprogram_counter() is
a heavyweight and high-frequency operation, especially when host disables
the watchdog (maximum 21000000 ns) which leads to an unacceptable latency
of the guest NMI handler. It limits the use of vPMUs in the guest.
When a vPMC is fully enabled, the legacy reprogram_*_counter() would stop
and release its existing perf_event (if any) every time EVEN in most cases
almost the same requested perf_event will be created and configured again.
For each vPMC, if the reuqested config ('u64 eventsel' for gp and 'u8 ctrl'
for fixed) is the same as its current config AND a new sample period based
on pmc->counter is accepted by host perf interface, the current event could
be reused safely as a new created one does. Otherwise, do release the
undesirable perf_event and reprogram a new one as usual.
It's light-weight to call pmc_pause_counter (disable, read and reset event)
and pmc_resume_counter (recalibrate period and re-enable event) as guest
expects instead of release-and-create again on any condition. Compared to
use the filterable event->attr or hw.config, a new 'u64 current_config'
field is added to save the last original programed config for each vPMC.
Based on this implementation, the number of calls to pmc_reprogram_counter
is reduced by ~82.5% for a gp sampling event and ~99.9% for a fixed event.
In the usage of multiplexing perf sampling mode, the average latency of the
guest NMI handler is reduced from 104923 ns to 48393 ns (~2.16x speed up).
If host disables watchdog, the minimum latecy of guest NMI handler could be
speed up at ~3413x (from 20407603 to 5979 ns) and at ~786x in the average.
Suggested-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
136 lines
4.1 KiB
C
136 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __KVM_X86_PMU_H
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#define __KVM_X86_PMU_H
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#define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu)
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#define pmu_to_vcpu(pmu) (container_of((pmu), struct kvm_vcpu, arch.pmu))
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#define pmc_to_pmu(pmc) (&(pmc)->vcpu->arch.pmu)
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/* retrieve the 4 bits for EN and PMI out of IA32_FIXED_CTR_CTRL */
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#define fixed_ctrl_field(ctrl_reg, idx) (((ctrl_reg) >> ((idx)*4)) & 0xf)
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#define VMWARE_BACKDOOR_PMC_HOST_TSC 0x10000
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#define VMWARE_BACKDOOR_PMC_REAL_TIME 0x10001
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#define VMWARE_BACKDOOR_PMC_APPARENT_TIME 0x10002
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struct kvm_event_hw_type_mapping {
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u8 eventsel;
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u8 unit_mask;
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unsigned event_type;
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};
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struct kvm_pmu_ops {
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unsigned (*find_arch_event)(struct kvm_pmu *pmu, u8 event_select,
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u8 unit_mask);
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unsigned (*find_fixed_event)(int idx);
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bool (*pmc_is_enabled)(struct kvm_pmc *pmc);
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struct kvm_pmc *(*pmc_idx_to_pmc)(struct kvm_pmu *pmu, int pmc_idx);
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struct kvm_pmc *(*rdpmc_ecx_to_pmc)(struct kvm_vcpu *vcpu,
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unsigned int idx, u64 *mask);
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struct kvm_pmc *(*msr_idx_to_pmc)(struct kvm_vcpu *vcpu, u32 msr);
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int (*is_valid_rdpmc_ecx)(struct kvm_vcpu *vcpu, unsigned int idx);
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bool (*is_valid_msr)(struct kvm_vcpu *vcpu, u32 msr);
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int (*get_msr)(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
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int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
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void (*refresh)(struct kvm_vcpu *vcpu);
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void (*init)(struct kvm_vcpu *vcpu);
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void (*reset)(struct kvm_vcpu *vcpu);
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};
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static inline u64 pmc_bitmask(struct kvm_pmc *pmc)
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{
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struct kvm_pmu *pmu = pmc_to_pmu(pmc);
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return pmu->counter_bitmask[pmc->type];
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}
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static inline u64 pmc_read_counter(struct kvm_pmc *pmc)
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{
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u64 counter, enabled, running;
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counter = pmc->counter;
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if (pmc->perf_event)
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counter += perf_event_read_value(pmc->perf_event,
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&enabled, &running);
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/* FIXME: Scaling needed? */
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return counter & pmc_bitmask(pmc);
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}
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static inline void pmc_release_perf_event(struct kvm_pmc *pmc)
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{
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if (pmc->perf_event) {
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perf_event_release_kernel(pmc->perf_event);
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pmc->perf_event = NULL;
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pmc->current_config = 0;
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}
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}
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static inline void pmc_stop_counter(struct kvm_pmc *pmc)
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{
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if (pmc->perf_event) {
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pmc->counter = pmc_read_counter(pmc);
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pmc_release_perf_event(pmc);
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}
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}
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static inline bool pmc_is_gp(struct kvm_pmc *pmc)
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{
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return pmc->type == KVM_PMC_GP;
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}
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static inline bool pmc_is_fixed(struct kvm_pmc *pmc)
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{
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return pmc->type == KVM_PMC_FIXED;
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}
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static inline bool pmc_is_enabled(struct kvm_pmc *pmc)
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{
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return kvm_x86_ops->pmu_ops->pmc_is_enabled(pmc);
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}
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/* returns general purpose PMC with the specified MSR. Note that it can be
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* used for both PERFCTRn and EVNTSELn; that is why it accepts base as a
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* paramenter to tell them apart.
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*/
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static inline struct kvm_pmc *get_gp_pmc(struct kvm_pmu *pmu, u32 msr,
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u32 base)
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{
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if (msr >= base && msr < base + pmu->nr_arch_gp_counters)
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return &pmu->gp_counters[msr - base];
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return NULL;
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}
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/* returns fixed PMC with the specified MSR */
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static inline struct kvm_pmc *get_fixed_pmc(struct kvm_pmu *pmu, u32 msr)
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{
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int base = MSR_CORE_PERF_FIXED_CTR0;
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if (msr >= base && msr < base + pmu->nr_arch_fixed_counters)
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return &pmu->fixed_counters[msr - base];
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return NULL;
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}
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void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel);
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void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 ctrl, int fixed_idx);
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void reprogram_counter(struct kvm_pmu *pmu, int pmc_idx);
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void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu);
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void kvm_pmu_handle_event(struct kvm_vcpu *vcpu);
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int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data);
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int kvm_pmu_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx);
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bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr);
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int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
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int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
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void kvm_pmu_refresh(struct kvm_vcpu *vcpu);
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void kvm_pmu_reset(struct kvm_vcpu *vcpu);
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void kvm_pmu_init(struct kvm_vcpu *vcpu);
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void kvm_pmu_destroy(struct kvm_vcpu *vcpu);
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int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp);
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bool is_vmware_backdoor_pmc(u32 pmc_idx);
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extern struct kvm_pmu_ops intel_pmu_ops;
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extern struct kvm_pmu_ops amd_pmu_ops;
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#endif /* __KVM_X86_PMU_H */
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