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a5890c12ec
Add microchip coreQSPI compatible string and update the title/description to reflect this addition. Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220808064603.1174906-2-nagasuresh.relli@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
56 lines
1.1 KiB
YAML
56 lines
1.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip FPGA {Q,}SPI Controllers
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description:
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SPI and QSPI controllers on Microchip PolarFire SoC and the "soft"/
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fabric IP cores they are based on
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maintainers:
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- Conor Dooley <conor.dooley@microchip.com>
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allOf:
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- $ref: spi-controller.yaml#
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properties:
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compatible:
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enum:
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- microchip,mpfs-spi
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- microchip,mpfs-qspi
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- microchip,coreqspi-rtl-v2 # FPGA QSPI
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clock-names:
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maxItems: 1
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clocks:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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unevaluatedProperties: false
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examples:
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- |
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#include "dt-bindings/clock/microchip,mpfs-clock.h"
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spi@20108000 {
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compatible = "microchip,mpfs-spi";
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reg = <0x20108000 0x1000>;
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clocks = <&clkcfg CLK_SPI0>;
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interrupt-parent = <&plic>;
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interrupts = <54>;
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};
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...
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