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	The SM6375 TLMM pin controller has GPIOs 0-155, so narrow the pattern and gpio-ranges in the example. Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230202104452.299048-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
		
			
				
	
	
		
			158 lines
		
	
	
	
		
			5.2 KiB
		
	
	
	
		
			YAML
		
	
	
	
	
	
			
		
		
	
	
			158 lines
		
	
	
	
		
			5.2 KiB
		
	
	
	
		
			YAML
		
	
	
	
	
	
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,sm6375-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. SM6375 TLMM block
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maintainers:
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  - Konrad Dybcio <konrad.dybcio@somainline.org>
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description:
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  Top Level Mode Multiplexer pin controller in Qualcomm SM6375 SoC.
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allOf:
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  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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  compatible:
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    const: qcom,sm6375-tlmm
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  reg:
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    maxItems: 1
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  interrupts:
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    maxItems: 1
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  interrupt-controller: true
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  "#interrupt-cells": true
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  gpio-controller: true
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  gpio-reserved-ranges: true
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  "#gpio-cells": true
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  gpio-ranges: true
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  wakeup-parent: true
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required:
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  - compatible
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  - reg
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additionalProperties: false
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patternProperties:
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  "-state$":
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    oneOf:
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      - $ref: "#/$defs/qcom-sm6375-tlmm-state"
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      - patternProperties:
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          "-pins$":
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            $ref: "#/$defs/qcom-sm6375-tlmm-state"
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        additionalProperties: false
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$defs:
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  qcom-sm6375-tlmm-state:
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    type: object
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    description:
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      Pinctrl node's client devices use subnodes for desired pin configuration.
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      Client device subnodes use below standard properties.
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    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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    properties:
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      pins:
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        description:
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          List of gpio pins affected by the properties specified in this
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          subnode.
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        items:
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          oneOf:
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            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$"
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            - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
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                      sdc2_cmd, sdc2_data ]
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        minItems: 1
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        maxItems: 36
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      function:
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        description:
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          Specify the alternative function to be configured for the specified
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          pins.
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        enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1,
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                atest_char2, atest_char3, atest_tsens, atest_tsens2,
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                atest_usb1, atest_usb10, atest_usb11, atest_usb12,
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                atest_usb13, atest_usb2, atest_usb20, atest_usb21,
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                atest_usb22, atest_usb23, audio_ref, btfm_slimbus, cam_mclk,
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                cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2,
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                cci_timer3, cci_timer4, cri_trng, dbg_out, ddr_bist,
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                ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd,
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                gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0, gp_pdm1, gp_pdm2, gpio,
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                gps_tx, ibi_i3c, jitter_bist, ldo_en, ldo_update, lpass_ext,
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                m_voc, mclk, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
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                mdp_vsync3, mi2s_0, mi2s_1, mi2s_2, mss_lte, nav_gpio,
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                nav_pps, pa_indicator, phase_flag0, phase_flag1, phase_flag10,
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                phase_flag11, phase_flag12, phase_flag13, phase_flag14,
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                phase_flag15, phase_flag16, phase_flag17, phase_flag18,
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                phase_flag19, phase_flag2, phase_flag20, phase_flag21,
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                phase_flag22, phase_flag23, phase_flag24, phase_flag25,
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                phase_flag26, phase_flag27, phase_flag28, phase_flag29,
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                phase_flag3, phase_flag30, phase_flag31, phase_flag4,
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                phase_flag5, phase_flag6, phase_flag7, phase_flag8,
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                phase_flag9, pll_bist, pll_bypassnl, pll_clk, pll_reset,
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                prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
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                qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11,
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                qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15,
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                qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6,
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                qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable,
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                qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
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                qlink1_wmss, qup00, qup01, qup02, qup10, qup11_f1, qup11_f2,
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                qup12, qup13_f1, qup13_f2, qup14, sd_write, sdc1_tb, sdc2_tb,
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                sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
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                tsense_pwm2, uim1_clk, uim1_data, uim1_present, uim1_reset,
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                uim2_clk, uim2_data, uim2_present, uim2_reset, usb2phy_ac,
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                usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1,
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                wlan2_adc0, wlan2_adc1 ]
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      bias-disable: true
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      bias-pull-down: true
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      bias-pull-up: true
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      drive-strength: true
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      input-enable: true
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      output-high: true
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      output-low: true
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    required:
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      - pins
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    additionalProperties: false
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examples:
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  - |
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    #include <dt-bindings/interrupt-controller/arm-gic.h>
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    pinctrl@500000 {
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        compatible = "qcom,sm6375-tlmm";
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        reg = <0x00500000 0x800000>;
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        interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
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        gpio-controller;
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        #gpio-cells = <2>;
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        interrupt-controller;
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        #interrupt-cells = <2>;
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        gpio-ranges = <&tlmm 0 0 157>; /* GPIOs + ufs_reset */
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        gpio-wo-subnode-state {
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            pins = "gpio1";
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            function = "gpio";
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        };
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        uart-w-subnodes-state {
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            rx-pins {
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                pins = "gpio18";
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                function = "qup13_f2";
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                bias-pull-up;
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            };
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            tx-pins {
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                pins = "gpio19";
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                function = "qup13_f2";
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                bias-disable;
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            };
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        };
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    };
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...
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