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27a22fbdee
Clang reports a warning on the __tlbi(aside1is, 0) macro expansion since
the value size does not match the register size specified in the inline
asm. Construct the ASID value using the __TLBI_VADDR() macro.
Fixes: 222fc0c850 ("arm64: compat: Workaround Neoverse-N1 #1542419 for compat user-space")
Reported-by: Nathan Chancellor <natechancellor@gmail.com>
Cc: James Morse <james.morse@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
120 lines
3 KiB
C
120 lines
3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Based on arch/arm/kernel/sys_arm.c
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*
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* Copyright (C) People who wrote linux/arch/i386/kernel/sys_i386.c
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* Copyright (C) 1995, 1996 Russell King.
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* Copyright (C) 2012 ARM Ltd.
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*/
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#include <linux/compat.h>
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#include <linux/cpufeature.h>
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#include <linux/personality.h>
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#include <linux/sched.h>
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#include <linux/sched/signal.h>
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#include <linux/slab.h>
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#include <linux/syscalls.h>
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#include <linux/uaccess.h>
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#include <asm/cacheflush.h>
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#include <asm/system_misc.h>
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#include <asm/tlbflush.h>
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#include <asm/unistd.h>
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static long
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__do_compat_cache_op(unsigned long start, unsigned long end)
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{
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long ret;
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do {
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unsigned long chunk = min(PAGE_SIZE, end - start);
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if (fatal_signal_pending(current))
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return 0;
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if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) {
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/*
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* The workaround requires an inner-shareable tlbi.
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* We pick the reserved-ASID to minimise the impact.
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*/
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__tlbi(aside1is, __TLBI_VADDR(0, 0));
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dsb(ish);
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}
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ret = __flush_cache_user_range(start, start + chunk);
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if (ret)
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return ret;
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cond_resched();
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start += chunk;
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} while (start < end);
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return 0;
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}
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static inline long
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do_compat_cache_op(unsigned long start, unsigned long end, int flags)
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{
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if (end < start || flags)
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return -EINVAL;
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if (!access_ok((const void __user *)start, end - start))
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return -EFAULT;
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return __do_compat_cache_op(start, end);
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}
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/*
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* Handle all unrecognised system calls.
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*/
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long compat_arm_syscall(struct pt_regs *regs, int scno)
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{
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void __user *addr;
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switch (scno) {
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/*
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* Flush a region from virtual address 'r0' to virtual address 'r1'
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* _exclusive_. There is no alignment requirement on either address;
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* user space does not need to know the hardware cache layout.
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*
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* r2 contains flags. It should ALWAYS be passed as ZERO until it
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* is defined to be something else. For now we ignore it, but may
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* the fires of hell burn in your belly if you break this rule. ;)
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*
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* (at a later date, we may want to allow this call to not flush
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* various aspects of the cache. Passing '0' will guarantee that
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* everything necessary gets flushed to maintain consistency in
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* the specified region).
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*/
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case __ARM_NR_compat_cacheflush:
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return do_compat_cache_op(regs->regs[0], regs->regs[1], regs->regs[2]);
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case __ARM_NR_compat_set_tls:
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current->thread.uw.tp_value = regs->regs[0];
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/*
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* Protect against register corruption from context switch.
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* See comment in tls_thread_flush.
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*/
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barrier();
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write_sysreg(regs->regs[0], tpidrro_el0);
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return 0;
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default:
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/*
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* Calls 0xf0xxx..0xf07ff are defined to return -ENOSYS
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* if not implemented, rather than raising SIGILL. This
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* way the calling program can gracefully determine whether
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* a feature is supported.
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*/
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if (scno < __ARM_NR_COMPAT_END)
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return -ENOSYS;
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break;
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}
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addr = (void __user *)instruction_pointer(regs) -
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(compat_thumb_mode(regs) ? 2 : 4);
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arm64_notify_die("Oops - bad compat syscall(2)", regs,
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SIGILL, ILL_ILLTRP, addr, scno);
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return 0;
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}
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