linux/drivers/gpu
Hanno Böck 9f58582c7a drm/i915: Properly sort MI coomand table
In the future, we may want to speed up command/register searching using
a bisection and so we require them to be in ascending order respectively
by command value or register address. However, this was not true for one
pair in the MI table; make it so.

Signed-off-by: Hanno Boeck <hanno@hboeck.de>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Hand-assemble patch from raw patch from Hanno and commit message from Chris.]
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
2015-07-29 10:29:58 +02:00
..
drm drm/i915: Properly sort MI coomand table 2015-07-29 10:29:58 +02:00
host1x
ipu-v3 GPU: ipu: Fix race in installing IPU chained IRQ handler 2015-06-18 14:03:08 +02:00
vga
Makefile