linux/arch/csky/mm
Guo Ren 9d35dc3006 csky: Revert mmu ASID mechanism
Current C-SKY ASID mechanism is from mips and it doesn't work well
with multi-cores. ASID per core mechanism is not suitable for C-SKY
SMP tlb maintain operations, eg: tlbi.vas need share the same asid
in all processors and it'll invalid the tlb entry in all cores with
the same asid.

This patch is prepare for new ASID mechanism.

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Cc: Arnd Bergmann <arnd@arndb.de>
2019-07-19 14:21:36 +08:00
..
cachev1.c csky: Cache and TLB routines 2018-10-25 23:36:19 +08:00
cachev2.c csky: Cache and TLB routines 2018-10-25 23:36:19 +08:00
dma-mapping.c csky: use the generic remapping dma alloc implementation 2018-12-01 18:07:16 +01:00
fault.c csky: Fixup compile warning 2019-04-22 14:46:23 +08:00
highmem.c treewide: add checks for the return value of memblock_alloc*() 2019-03-12 10:04:02 -07:00
init.c csky: Revert mmu ASID mechanism 2019-07-19 14:21:36 +08:00
ioremap.c csky: Fixup io-range page attribute for mmap("/dev/mem") 2019-02-13 09:48:14 +08:00
Makefile treewide: Add SPDX license identifier - Makefile/Kconfig 2019-05-21 10:50:46 +02:00
syscache.c csky: Cache and TLB routines 2018-10-25 23:36:19 +08:00
tlb.c csky: Revert mmu ASID mechanism 2019-07-19 14:21:36 +08:00