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9bdcf336d0
All Alchemy development boards have external CPLDs with a few registers in them. They all share an identical register layout with only a few minor differences (except the PB1000) in bit functions and base addresses. This patch - adds a primitive facility to initialize and use these external registers, - replaces all occurrences of bcsr->xxx accesses with calls to the new functions (the pb1200 cascade irq handling code is special). - collects BCSR register information scattered throughout the board headers in a central place. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
144 lines
4.5 KiB
C
144 lines
4.5 KiB
C
/*
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* BRIEF MODULE DESCRIPTION
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* Au1xxx irq map table
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <asm/mach-au1x00/au1000.h>
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#ifdef CONFIG_MIPS_PB1200
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#include <asm/mach-pb1x00/pb1200.h>
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#endif
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#ifdef CONFIG_MIPS_DB1200
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#include <asm/mach-db1x00/db1200.h>
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#define PB1200_INT_BEGIN DB1200_INT_BEGIN
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#define PB1200_INT_END DB1200_INT_END
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#endif
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#include <asm/mach-db1x00/bcsr.h>
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struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
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/* This is external interrupt cascade */
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{ AU1000_GPIO_7, IRQF_TRIGGER_LOW, 0 },
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};
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static void __iomem *bcsr_virt;
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/*
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* Support for External interrupts on the Pb1200 Development platform.
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*/
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static void pb1200_cascade_handler(unsigned int irq, struct irq_desc *d)
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{
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unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);
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for ( ; bisr; bisr &= bisr - 1)
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generic_handle_irq(PB1200_INT_BEGIN + __ffs(bisr));
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}
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/* NOTE: both the enable and mask bits must be cleared, otherwise the
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* CPLD generates tons of spurious interrupts (at least on the DB1200).
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*/
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static void pb1200_mask_irq(unsigned int irq_nr)
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{
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unsigned short v = 1 << (irq_nr - PB1200_INT_BEGIN);
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__raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);
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__raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
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wmb();
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}
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static void pb1200_maskack_irq(unsigned int irq_nr)
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{
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unsigned short v = 1 << (irq_nr - PB1200_INT_BEGIN);
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__raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);
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__raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
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__raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */
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wmb();
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}
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static void pb1200_unmask_irq(unsigned int irq_nr)
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{
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unsigned short v = 1 << (irq_nr - PB1200_INT_BEGIN);
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__raw_writew(v, bcsr_virt + BCSR_REG_INTSET);
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__raw_writew(v, bcsr_virt + BCSR_REG_MASKSET);
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wmb();
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}
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static struct irq_chip pb1200_cpld_irq_type = {
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#ifdef CONFIG_MIPS_PB1200
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.name = "Pb1200 Ext",
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#endif
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#ifdef CONFIG_MIPS_DB1200
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.name = "Db1200 Ext",
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#endif
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.mask = pb1200_mask_irq,
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.mask_ack = pb1200_maskack_irq,
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.unmask = pb1200_unmask_irq,
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};
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void __init board_init_irq(void)
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{
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unsigned int irq;
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au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
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#ifdef CONFIG_MIPS_PB1200
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bcsr_virt = (void __iomem *)KSEG1ADDR(PB1200_BCSR_PHYS_ADDR);
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/* We have a problem with CPLD rev 3. */
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if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
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printk(KERN_ERR "WARNING!!!\n");
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printk(KERN_ERR "WARNING!!!\n");
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printk(KERN_ERR "WARNING!!!\n");
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printk(KERN_ERR "WARNING!!!\n");
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printk(KERN_ERR "WARNING!!!\n");
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printk(KERN_ERR "WARNING!!!\n");
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printk(KERN_ERR "Pb1200 must be at CPLD rev 4. Please have Pb1200\n");
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printk(KERN_ERR "updated to latest revision. This software will\n");
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printk(KERN_ERR "not work on anything less than CPLD rev 4.\n");
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printk(KERN_ERR "WARNING!!!\n");
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printk(KERN_ERR "WARNING!!!\n");
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printk(KERN_ERR "WARNING!!!\n");
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printk(KERN_ERR "WARNING!!!\n");
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printk(KERN_ERR "WARNING!!!\n");
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printk(KERN_ERR "WARNING!!!\n");
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panic("Game over. Your score is 0.");
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}
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#else
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bcsr_virt = (void __iomem *)KSEG1ADDR(DB1200_BCSR_PHYS_ADDR);
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#endif
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/* mask & disable & ack all */
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bcsr_write(BCSR_INTCLR, 0xffff);
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bcsr_write(BCSR_MASKCLR, 0xffff);
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bcsr_write(BCSR_INTSTAT, 0xffff);
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for (irq = PB1200_INT_BEGIN; irq <= PB1200_INT_END; irq++)
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set_irq_chip_and_handler_name(irq, &pb1200_cpld_irq_type,
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handle_level_irq, "level");
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set_irq_chained_handler(AU1000_GPIO_7, pb1200_cascade_handler);
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}
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