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df72c23ea2
This patch adds the device tree support for FSL LS2088A SoC based on
ARMv8 architecture.
Following levels of DTSI/DTS files have been created for the LS2088A
SoC family:
- fsl-ls2088a.dtsi:
DTS-Include file for FSL LS2088A SoC.
- fsl-ls2088a-qds.dts:
DTS file for FSL LS2088A QDS board.
- fsl-ls2088a-rdb.dts:
DTS file for FSL LS2088A RDB board.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
165 lines
4.7 KiB
Text
165 lines
4.7 KiB
Text
/*
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* Device Tree Include file for Freescale Layerscape-2088A family SoC.
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*
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* Copyright (C) 2016-17, Freescale Semiconductor
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*
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* Abhimanyu Saini <abhimanyu.saini@nxp.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPLv2 or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "fsl-ls208xa.dtsi"
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&cpu {
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x0>;
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clocks = <&clockgen 1 0>;
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next-level-cache = <&cluster0_l2>;
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#cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x1>;
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clocks = <&clockgen 1 0>;
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next-level-cache = <&cluster0_l2>;
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};
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cpu2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x100>;
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clocks = <&clockgen 1 1>;
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next-level-cache = <&cluster1_l2>;
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#cooling-cells = <2>;
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};
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cpu3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x101>;
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clocks = <&clockgen 1 1>;
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next-level-cache = <&cluster1_l2>;
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};
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cpu4: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x200>;
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clocks = <&clockgen 1 2>;
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next-level-cache = <&cluster2_l2>;
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#cooling-cells = <2>;
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};
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cpu5: cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x201>;
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clocks = <&clockgen 1 2>;
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next-level-cache = <&cluster2_l2>;
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};
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cpu6: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x300>;
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clocks = <&clockgen 1 3>;
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next-level-cache = <&cluster3_l2>;
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#cooling-cells = <2>;
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};
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cpu7: cpu@301 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x301>;
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clocks = <&clockgen 1 3>;
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next-level-cache = <&cluster3_l2>;
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};
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cluster0_l2: l2-cache0 {
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compatible = "cache";
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};
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cluster1_l2: l2-cache1 {
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compatible = "cache";
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};
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cluster2_l2: l2-cache2 {
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compatible = "cache";
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};
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cluster3_l2: l2-cache3 {
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compatible = "cache";
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};
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};
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&pcie1 {
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reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
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0x20 0x00000000 0x0 0x00002000>; /* configuration space */
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ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000
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0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>;
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};
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&pcie2 {
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reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
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0x28 0x00000000 0x0 0x00002000>; /* configuration space */
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ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000
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0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>;
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};
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&pcie3 {
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reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
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0x30 0x00000000 0x0 0x00002000>; /* configuration space */
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ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000
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0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>;
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};
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&pcie4 {
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reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
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0x38 0x00000000 0x0 0x00002000>; /* configuration space */
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ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000
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0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>;
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};
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