Taimur Hassan 99d1437aa0 drm/amd/display: Check for flip pending before locking pipes. ... [Why] When running a game/benchmark with v-sync disabled, disabling a plane (which is v-sync) can cause an underflow. This is due to flips that are pending before pipe locking being applied after locks are released and pipes have been re-arranged or disconnected. This can potentially apply a flip on the incorrect pipe. [How] Check that any pending flips are cleared before locking any pipes to ensure flips are applied on the correct pipes. Signed-off-by: Taimur Hassan <syed.hassan@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-09-22 12:28:56 -04:00
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hw	drm/amd/display: Rename set_mst_bandwidth to align with DP spec	2020-09-15 17:52:41 -04:00
bw_fixed.h
clock_source.h
compressor.h
core_status.h	drm/amd/display: Add helper to convert DC status	2020-07-01 01:59:20 -04:00
core_types.h	drm/amd/display: implement notify stream mask	2020-09-15 17:52:41 -04:00
custom_float.h
dc_link_ddc.h	drm/amd/display: DP link layer test 4.2.1.1 fix due to specs update	2020-07-01 01:59:26 -04:00
dc_link_dp.h	drm/amd/display: DP link layer test 4.2.1.1 fix due to specs update	2020-07-01 01:59:26 -04:00
dce_calcs.h
dcn_calc_math.h
dcn_calcs.h
hw_sequencer.h	drm/amd/display: Check for flip pending before locking pipes.	2020-09-22 12:28:56 -04:00
hw_sequencer_private.h	drm/amd/display: move panel power seq to new panel struct	2020-04-22 18:11:48 -04:00
link_hwss.h
reg_helper.h
resource.h	drm/amd/display: Add DCN3 Resource	2020-07-01 01:59:15 -04:00
vm_helper.h