Dale Zhao 8edb94562a drm/amd/display: WA to ensure MUX chip gets SUPPORTED_LINK_RATES of eDP ... [Why] Customer make a request to add this WA by driver. Some MUX chips will power down with eDP 1.4 panel and lose previous supported link rates(DPCD 0x010) in customer's hybrid-GPU designs. As a result, during sleep resuming and screen turns on from idle, link training will be performed incorrectly and eDP will flicker or black screen. These MUX chips need source to read DPCD 0x010 again during LKT so that it can restore supported link rates of panel. For driver side, supported link rate set is fetched when link detection, no need to update but just read again as WA. [How] Read DPCD 0x010 again during link training for eDP 1.4. Signed-off-by: Dale Zhao <dale.zhao@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-11-02 15:31:51 -05:00
..
acp
amdgpu	amd/amdgpu: Disable VCN DPG mode for Picasso	2020-11-01 20:01:56 -05:00
amdkfd	drm/amdkfd: Fix getting unique_id in topology	2020-10-30 00:59:42 -04:00
display	drm/amd/display: WA to ensure MUX chip gets SUPPORTED_LINK_RATES of eDP	2020-11-02 15:31:51 -05:00
include	drm/amdgpu: drop CONFIG_DRM_AMD_DC_DCN3_01 from atomfirmware.h	2020-10-30 01:02:10 -04:00
pm	drm/amd/pm: fix compile warnings about variable used uninitialized	2020-10-30 14:27:15 -04:00