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1fadf42ed5
soc15 asics have a new vbios interface. These headers define that interface. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
86 lines
3.2 KiB
C
86 lines
3.2 KiB
C
/****************************************************************************\
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*
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* File Name atomfirmwareid.h
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*
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* Description ATOM BIOS command/data table ID definition header file
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*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
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* and associated documentation files (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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\****************************************************************************/
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#ifndef _ATOMFIRMWAREID_H_
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#define _ATOMFIRMWAREID_H_
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enum atom_master_data_table_id
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{
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VBIOS_DATA_TBL_ID__UTILITY_PIPELINE,
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VBIOS_DATA_TBL_ID__MULTIMEDIA_INF,
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VBIOS_DATA_TBL_ID__FIRMWARE_INF,
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VBIOS_DATA_TBL_ID__LCD_INF,
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VBIOS_DATA_TBL_ID__SMU_INF,
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VBIOS_DATA_TBL_ID__VRAM_USAGE_BY_FIRMWARE,
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VBIOS_DATA_TBL_ID__GPIO_PIN_LUT,
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VBIOS_DATA_TBL_ID__GFX_INF,
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VBIOS_DATA_TBL_ID__POWER_PLAY_INF,
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VBIOS_DATA_TBL_ID__DISPLAY_OBJECT_INF,
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VBIOS_DATA_TBL_ID__INDIRECT_IO_ACCESS,
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VBIOS_DATA_TBL_ID__UMC_INF,
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VBIOS_DATA_TBL_ID__DCE_INF,
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VBIOS_DATA_TBL_ID__VRAM_INF,
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VBIOS_DATA_TBL_ID__INTEGRATED_SYS_INF,
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VBIOS_DATA_TBL_ID__ASIC_PROFILING_INF,
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VBIOS_DATA_TBL_ID__VOLTAGE_OBJ_INF,
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VBIOS_DATA_TBL_ID__UNDEFINED,
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};
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enum atom_master_command_table_id
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{
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VBIOS_CMD_TBL_ID__ASIC_INIT,
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VBIOS_CMD_TBL_ID__DIGX_ENCODER_CONTROL,
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VBIOS_CMD_TBL_ID__SET_ENGINE_CLOCK,
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VBIOS_CMD_TBL_ID__SET_MEMORY_CLOCK,
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VBIOS_CMD_TBL_ID__SET_PIXEL_CLOCK,
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VBIOS_CMD_TBL_ID__ENABLE_DISP_POWER_GATING,
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VBIOS_CMD_TBL_ID__BLANK_CRTC,
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VBIOS_CMD_TBL_ID__ENABLE_CRTC,
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VBIOS_CMD_TBL_ID__GET_SMU_CLOCK_INFO,
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VBIOS_CMD_TBL_ID__SELECT_CRTC_SOURCE,
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VBIOS_CMD_TBL_ID__SET_DCE_CLOCK,
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VBIOS_CMD_TBL_ID__GET_MEMORY_CLOCK,
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VBIOS_CMD_TBL_ID__GET_ENGINE_CLOCK,
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VBIOS_CMD_TBL_ID__SET_CRTC_USING_DTD_TIMING,
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VBIOS_CMD_TBL_ID__EXTENAL_ENCODER_CONTROL,
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VBIOS_CMD_TBL_ID__PROCESS_I2C_CHANNEL_TRANSACTION,
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VBIOS_CMD_TBL_ID__COMPUTE_GPU_CLOCK_PARAM,
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VBIOS_CMD_TBL_ID__DYNAMIC_MEMORY_SETTINGS,
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VBIOS_CMD_TBL_ID__MEMORY_TRAINING,
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VBIOS_CMD_TBL_ID__SET_VOLTAGE,
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VBIOS_CMD_TBL_ID__DIG1_TRANSMITTER_CONTROL,
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VBIOS_CMD_TBL_ID__PROCESS_AUX_CHANNEL_TRANSACTION,
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VBIOS_CMD_TBL_ID__GET_VOLTAGE_INF,
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VBIOS_CMD_TBL_ID__UNDEFINED,
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};
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#endif /* _ATOMFIRMWAREID_H_ */
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/* ### EOF ### */
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